AMD Versal Adaptive SoC Solutions
Systems leveraging implementations of the PCI Express® specification are pervasive in data center, communications, and embedded applications. The multiple connectivity options available in the Versal™ architecture directly support users’ needs to focus on their core competency while leveraging advanced standards-based interfaces. The integrated blocks for PCI Express in the Versal architecture offer premium performance levels with ease of use and efficiency over fully soft IP solutions. The Versal architecture integrates five types of integrated blocks for PCI Express:
- MDB5: integrated block for PCI Express Rev. 5.0 with DMA/bridge
- CPM5: integrated block for PCI Express Rev. 5.0 with DMA/bridge
- PL PCIE5: integrated block for PCI Express Rev. 5.0
- CPM4: integrated block for PCI Express Rev. 4.0 with DMA/bridge
- PL PCIE4: integrated block for PCI Express Rev. 4.0
MDB5, CPM5, PL PCIE5, CPM4, and PL PCIE4, in conjunction with available GTYP and GTY transceivers, enable interface operation at specification-defined data rates. These range from 2.5 GT/s per lane with one lane (Gen1x1) up to their rated maximum link configurations, with some integrated blocks reaching 32 GT/s per lane with 8 lanes (Gen5x8) and 16 GT/s per lane with 16 lanes (Gen4x16).
The table below is a summary of key characteristics of the integrated blocks for PCI Express in the Versal architecture. Refer to the Versal Architecture and Product Data Sheet: Overview (DS950) for additional information on available resources and capabilities based on orderable device, package, and speed/voltage grade combinations.
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Versal Architecture Integrated Blocks for PCI Express |
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MDB5
View Diagram
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CPM5
View Diagram
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PL PCIE5
View Diagram
|
CPM4
View Diagram
|
PL PCIE4
View Diagram
|
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Associated
Specifications |
PCIe Rev. 5.0 |
PCIe Rev. 5.0 |
PCIe Rev. 5.0
|
PCIe Rev. 4.0
|
PCIe Rev. 4.0 |
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Max PCIe
Link Configs |
Gen5x4
2 x Gen5x2
Gen5x2 |
2 x Gen5x8
Gen4x16
2 x Gen4x8 |
Gen5x4
Gen4x8
Gen3x16 |
Gen4x16
2 x Gen4x8 |
Gen4x8
Gen3x16 |
---|
PCIe Port
Type Support |
EP, RP |
EP, RP,
Switch |
EP, RP,
Switch |
EP, RP,
Switch |
EP, RP,
Switch |
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Key PCIe
Features |
SR-IOV
8PF / 64VF |
SR-IOV
16PF / 4KVF |
SR-IOV
8PF / 4KVF |
SR-IOV
4PF / 252VF |
SR-IOV
4PF / 252VF |
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Integrated DMA/Bridge |
Two Bridges Required,
Two Optional DMAs |
Two Optional
QDMA/Bridge |
- |
One Optional
QDMA/Bridge or XDMA/Bridge |
- |
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MDB5, CPM5, PL PCIE5, CPM4, and PL PCIE4 can be used at reduced link configurations to optimize product designs for cost, support novel form factors, alleviate board complexity, and shrink power budgets. Additionally, reduced link configurations can support lower programmable logic resource utilization, depending on the nature of any soft IP solutions used to expand the application-level capabilities of these integrated blocks. CPM5, PL PCIE5, CPM4, and PL PCIE4 can be configured as Endpoint (EP), Root Port (RP), and switch port types. MDB5 can be configured as Endpoint (EP) and Root Port (RP) port types.
Pre-verified high-performance DMA/bridge subsystems for the integrated blocks for PCI Express in the Versal architecture enable users to focus design investment in their areas of greatest value. Available DMA/bridge subsystems include:
- MDB5 contains two controllers for PCI Express and integrates two instances of a DMA/bridge subsystem. Use of the integrated DMA is optional, and each instance is independently customizable. The DMA subsystems provide a tight coupling to integrated processors and the AXI interconnect. The subsystems also include bridge functionality. Data can be moved with memory-mapped techniques, including the programmable network on chip (NoC).
- CPM5 contains two controllers for PCI Express and also integrates two instances of a QDMA/bridge subsystem. Use of the integrated DMA is optional, and each instance is independently customizable. The QDMA subsystems provide scalable queue-based DMA for moving enormous volumes of data with low latency, plus support for multiple physical and virtual functions commonly required by enterprise class products. Data can be moved with memory-mapped techniques, including the programmable network on chip (NoC), or with streaming techniques, into the Versal adaptive SoC’s programmable logic. The subsystems also include bridge functionality to the AXI interconnect.
- CPM4 contains two controllers for PCI Express and also integrates one instance of a QDMA/XDMA/bridge subsystem. Use of the integrated DMA is optional, and when used, can be configured as a QDMA subsystem like that in the CPM5 or as an XDMA subsystem. Data can be moved with memory-mapped techniques, including the programmable NoC, or with streaming techniques, into the Versal adaptive SoC’s programmable logic. The subsystem also includes bridge functionality to the AXI interconnect.
- PL PCIE5 and PL PCIE4 are individual controllers for PCI Express and are supported by soft IP implementations of DMA/bridge subsystems available from AMD through the Vivado™ Design Suite IP catalog, and additional solutions are available from AMD Adaptive Computing Partners.
For most users, available DMA/bridge subsystems can provide time-saving infrastructure, enabling high-performance turnkey data movement. See the Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347), the Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344), and the AXI Bridge with DMA for PCIe solution from AMD Adaptive Computing Partner Smartlogic GmbH.
For users seeking to attach their own DMA/bridge subsystem—for preserving their driver and application software investment or to customize or optimize functionality using intimate knowledge of the end application—options are available to design directly to the controllers for PCI Express in the CPM5, PL PCIE5, CPM4, and PL PCIE4 blocks. See the Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346) and the Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343). For ultimate freedom to implement fully custom solutions, AMD offers a soft IP core PHY for PCI Express, enabling designers to attach their own controllers for PCI Express to available GTYP and GTY transceivers. AMD Adaptive Computing Partners, including Fidus Systems, Inc., offer development and consulting services with unique value propositions to differentiate and accelerate design with Versal adaptive SoCs.