Spartan-3A DSP

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Document
Document Type: Data Sheets
This is the data sheet for the CAN v3.2 core.
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Document Type: Data Sheets
The LogiCORE IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mbps Ethernet MAC, 1 Gbps Ethernet MAC and the 10/100 Mbps Ethernet MAC IP core. All cores support half-duplex and full-duplex operation.
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Document Type: Data Sheets
The LogiCORE IP Ethernet Statistics core provides a user-configurable collection of statistical counters that can be used to gather network traffic statistics for Xilinx Ethernet Media Access Controller (MAC) products.
Document
Document Type: Data Sheets
The Xilinx DVB-S.2 FEC Encoder core provides designers with a Forward Error Correction (FEC) Encoding block for DVB-S.2 systems.
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Document Type: Data Sheets
The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units, as well as an optional DCR (Device Control Register) slave interface to provide access to its bus error status registers.
Document
Document Type: Data Sheets
The PLBV46 Master Burst is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE products. It provides a bi-directional interface between a User IP core and the PLB v4.6 bus standard. This version of the PLBV46 Master Burst has been designed for PLBV46 Master operations consisting of single data beat read or write transfers and Fixed Length Burst Transfers of 2 to 16 data beats.
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Document Type: Data Sheets
DS610: Spartan-3A DSP FPGA Family Data Sheet
Document
Document Type: Data Sheets
This is the data sheet for the 3GPP Downlink Chip Rate v1.0 core.
Document
Document Type: Data Sheets
The IEEE 802.16e CTC decoder core performs iterative decoding of channel data that has been encoded as described in Section 8.4.9.2.3 of the IEEE Std 802.16e-2005 specification and corrigendum IEEE P802.16Rev2/D0b (June 2007).
Document
Document Type: Data Sheets
Presents an overview of the Extended Spartan-3A family
Document
Document Type: Data Sheets
The Xilinx Gamma Correction LogiCORE provides customers with an optimized hardware block for manipulating image data to match the response of display devices. This core is implemented using a lookup table structure that is programmed to implement a gamma correction curve transform on the input image data.
Document
Document Type: Data Sheets
The Xilinx LogiCORE IP Color Correction Matrix core is a 3 x 3 programmable coefficient matrix multiplier with offset compensation. This core can be used for color correction operations such as adjusting white balance, color cast, brightness, and/or contrast in an RGB image.
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Document Type: Data Sheets
The Xilinx LogiCORE Defective Pixel Correction solution is a dynamic solution that removes defective pixels from a camera image sensor array.
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Document Type: Data Sheets
The Xilinx Color Filter Array Interpolation IP LogiCORE provides an optimized hardware block to reconstruct sub-sampled color data for images captured by an image sensor fitted with a Bayer Color Filter Array. The color filter array overlaid over the silicon substrate enables CMOS or CCD image sensors to measure local light intensities corresponding to different wavelengths.
Document
Document Type: Data Sheets
The Xilinx Video Scaler LogiCORE IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis.
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Document Type: Data Sheets
The Xilinx Image Characterization LogiCORE IP calculates important statistical data for video input streams. The Image Characterization LogiCORE is an important processing block for many applications including face recognition and object detection.
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Document Type: Data Sheets
The Xilinx Video Timing Controller LogiCORE IP is a general purpose video timing generator and detector.
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Document Type: Data Sheets
The Xilinx Motion Adaptive Noise Reduction (MANR) LogiCORE IP is a module for both motion detection and motion adaptive noise reduction in video systems. The core allows the motion detection function to be used independently of the noise reduction function for applications where noise reduction is not needed.
Document
Document Type: Data Sheets
The Xilinx Image Noise Reduction LogiCORE provides users with an easy to use IP block for reducing noise within each frame of video. The core has a programmable, edge-adaptive smoothing function to change the characteristics of the filtering in real-time.
Document
Document Type: Data Sheets
The Xilinx Image Statistics LogiCORE IP implements the computationally intensive metering functionality common in digital cameras, camcorders and imaging devices. This core generates a set of statistics for color histograms, mean and variance values, edge and frequency content for 16 user-defined zones on a per frame basis.
Document
Document Type: Data Sheets
The Xilinx Image Edge Enhancement LogiCORE IP provides users with an easy-to-use IP block to enhance the edges of objects within each frame of video. The core provides a set of standard Sobel and Laplacian filters with programmable gain that adjust the strength of the edge enhancement effect.
Document
Document Type: Data Sheets
The Xilinx Video Scaler LogiCORE IP is an optimized hardware block that converts an input color image of one size to an output image of a different size. This highly configurable core supports in-system programmability on a frame basis. System design is made easier through support of both streaming-video and frame buffer-based interfaces. This core is designed to connect via an AXI4-Lite interface.
Document
Document Type: Data Sheets
The Xilinx Motion Adaptive Noise Reduction (MANR) LogiCORE IP is a module for both motion detection and motion adaptive noise reduction in video systems. This document contains information about the AXI4 version of the core.
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Document Type: Data Sheets
The Xilinx Video Timing Controller LogiCORE IP is a general purpose video timing generator and detector. This document contains information about the AXI4 version of the core.
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Document Type: Package Specifications
FG676/FGG676 drawing showing corner gate mold (CGM) and pin gate mold (PGM) options.
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Document Type: Package Specifications
FGG676 Material Declaration Data Sheet
Associated File(s):
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Document Type: Package Specifications
FG676 Material Declaration Data Sheet
Associated File(s):
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Document Type: Package Specifications
Package drawing for 484-ball Laminate Chip Scale BGA (CS484/CSG484)
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Document Type: Package Specifications
CS484 Material Declaration Data Sheet
Associated File(s):
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Document Type: Package Specifications
CSG484 Material Declaration Data Sheet
Associated File(s):
Results 1-30 of 121