This is the data sheet for the CAN v3.2 core.

The LogiCORE IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mbps Ethernet MAC, 1 Gbps Ethernet MAC and the 10/100 Mbps Ethernet MAC IP core. All cores support half-duplex and full-duplex operation.

Spartan®-3E FPGA Family Data Sheet (all four modules).

The LogiCORE IP Ethernet Statistics core provides a user-configurable collection of statistical counters that can be used to gather network traffic statistics for Xilinx Ethernet Media Access Controller (MAC) products.

This is the data sheet for the 802.16e CTC Encoder v3.0 core

The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units, as well as an optional DCR (Device Control Register) slave interface to provide access to its bus error status registers.

The PLBV46 Master Burst is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE products. It provides a bi-directional interface between a User IP core and the PLB v4.6 bus standard. This version of the PLBV46 Master Burst has been designed for PLBV46 Master operations consisting of single data beat read or write transfers and Fixed Length Burst Transfers of 2 to 16 data beats.

This is the data sheet for the H.264 Deblocker Core v1.0 core.

The CIC Compiler core provides the ability to design and implement Cascaded Integrator-Comb (CIC) filters for a variety of Xilinx FPGA devices.

The IEEE 802.16e CTC decoder core performs iterative decoding of channel data that has been encoded as described in Section 8.4.9.2.3 of the IEEE Std 802.16e-2005 specification and corrigendum IEEE P802.16Rev2/D0b (June 2007).

The LogiCORE IP Ethernet AVB core delivers a flexible solution to enhance standard Ethernet MAC functionality, providing prioritized channels through an existing MAC designed to supply a reliable, low latency, quality of service for live audio or video data. The core is designed to emerging IEEE802.1 standards from the Audio/Video Bridging (AVB) Task Group.

All errata items previously described in earlier revisions of this notice were integrated into the Spartan-3E data sheet as the Stepping 0 production device. See “Production Stepping” section in the data sheet for additional information.

See “Production Stepping” section in the data sheet for additional information.

All errata items previously described in earlier revisions of this notice were integrated into the Spartan™-3E data sheet as the Stepping 0 production device. See “Production Stepping” section in the data sheet for additional information.

See “Production Stepping” section in the data sheet for additional information.

See “Production Stepping” section in the data sheet for additional information.

Package drawing for 100-Pin Plastic Very Thing QFP (VQ100/VQG100)

FT256/FTG256 - Package Drawing (Fine-Pitch Thin BGA)

FG320/FGG320 drawing showing corner gate mold (CGM) and pin gate mold (PGM) options.

FG484/FGG484 drawing showing corner gate mold (CGM) and pin gate mold (PGM) options.

FG400/FGG400 drawing showing corner gate mold (CGM) and pin gate mold (PGM) options.

CPG132 - Material Declaration Data Sheet (Pb-free Chip Scale BGA)

FGG320 - Material Declaration Data Sheet (Pb-free Fine-Pitch BGA)

Material Declaration Data Sheet for FGG400

FGG484 Material Declaration Data Sheet (Pb-free)

Package name Material Declaration Data Sheet (Pb-free Plastic Flip-Chip BGA)

VQG100 - Material Declaration Data Sheet (Pb-free VQFP)

CP132 Material Declaration Data Sheet (Standard Chip Scale BGA)

FG320 - Material Declaration Data Sheet (Standard Fine-Pitch BGA)

FT256 Material Declaration Data Sheet