Timing - Critical Path

Description

The tool is informing the issue of a possible critical path which is leading to timing violation in the user code.

Explanation

A timing violation is a path of operations requiring more time than the available clock cycle. Each operation may constitute a certain delay in the hardware, and if a set of operations delays exceed the clock boundary the hls tool will inform the user of the violating clock cycle. If the design violates the clock cycle then the overall clock frequency rescales to the factor it could accommodate the operations. At HLS level these delays are only estimated.

One of the main reasons for a timing violation is because of the II constraint. If the user specifies a strict II-1 constraint in the user code then the tool packs the operations back to back inside a clock boundary to achieve the required II. If a single operation in the user code exceeds the clock boundary then the tool will issue a timing violation.

To view a timing violation in the user code, see Schedule Viewer.

Solution

The solution to the timing violation is to relax the II constraint or refactor the user code to break the timing path.