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The Virtex™ 6 FPGA Connectivity Kit is a comprehensive high performance connectivity development, debug and demonstration platform for high-bandwidth and high-performance applications in multiple market segments.
This development kit has been discontinued and is no longer offered for sale. The solutions targeted for this product will not be updated moving forward with limited support available from AMD.
The Virtex™ 6 FPGA Connectivity Kit is a comprehensive high performance connectivity development, debug and demonstration platform for high-bandwidth and high-performance applications in multiple market segments. The Virtex 6 FPGA Connectivity Kit delivers a fully validated and supported reference design that integrates built-in blocks for GTX transceivers and PCI Express, soft IP for XAUI protocol, a high-performance 10G DMA IP core from Northwest Logic, and a Virtual FIFO memory controller interfacing to an external DDR3 memory.
Jump-start your development with Targeted Reference Designs with support for the AXI4™ Interconnect Standard.
Featuring the Virtex 6 XC6VLX240T-1FFG1156 FPGA
Logic Cells | 241,152 |
---|---|
Memory (Kb) | 14,976 |
DSP Slices | 3,650 |
Maximum Transceivers (GTX) | 24 |
Max User I/O | 720 |
Featuring the ML605 Evaluation Board
Featuring the Virtex 6 LX240T FPGA
Device-locked to the Virtex 6 LX240T FPGA
Name | Description | License Type |
---|---|---|
Memory Interface Generator (MIG) | MIG is a free software tool used to generate memory controllers and interfaces for AMD FPGAs. | No-Charge IP |
Virtex 6 Integrated Block for PCI Express (PCIe) | AMD provides a Virtex 6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex 6 FPGA Integrated Block for PCIe FPGA and includes additional logic to create a complete solution for PCIe. | No-Charge IP |
XAUI/DXAUI | The AMD 10 Gigabit Attachment Unit Interface (XAUI) LogiCORE™ IP provides a 4-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. | No-Charge IP |