Overview

Verification and HW Debug is critical to ensure the functionality, performance, and reliability of the final FPGA implementation. Vivado’s verification features enable efficient validation of design functionality while its comprehensive debugging features empower engineers to efficiently locate and resolve issues within complex FPGA designs.

Features

Simulation Flow

AMD Vivado™ Design Suite provides an array of design entry, timing analysis, hardware debug, and simulation capabilities all encompassed in a single state of the art integrated design environment (IDE). This flow enables both the integrated and enterprise verification needs for all supported simulators.

Vivado enables behavioral, post-synthesis and post-implementation (functional or timing) simulations for the fully integrated Vivado Simulator and 3rd party HDL simulators. Time spent on simulation early in the design cycle helps identify issues early and significantly reduces turnaround times compared to later stages of the flow.

To aid flexibility in user verification environments, Vivado provides support for both an integrated environment as well as provides scripts to use with external verification setups.

The Vivado IDE supports all major simulators in integrated mode for interactive simulation users and script mode for advanced verification engineers.

Aldec - Active-HDL® & Riviera-PRO®, Cadence Xcelium® Simulator, Siemens EDA – ModelSim® & Questasim®, Synopsys VCS® and AMD Vivado Simulator

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AMD Vivado Simulation Flows

  • Key Features

    Simulation Features
    • Simulation flows provide the ability to compile simulation libraries for the supported simulators in the users’ environment to enable re-use of compiled libraries.
    • Ability to simulate and verify design integrity at different stages of the design process such as behavioral, post -synthesis functional and timing simulation and Post-implementation functional and timing simulation.
    • Unified simulation integration using consistent 3 step process (compile, elaborate, simulate) for all simulators
    • Simulation script generation for enterprise 3rd party simulators to enable verification using users own environments.

Vivado Simulator

Vivado™ Simulator is a feature-rich, mixed-language simulator that supports Verilog, SystemVerilog, and VHDL language. Vivado Simulator is included is part of Vivado and it is available at no additional cost. It does not have a design size, instances, or line limitation and it allows to run of unlimited instances of mixed-language simulation using a single Vivado license.

Vivado Simulator supports both Windows® and Linux® operating systems with powerful debugging features that are aimed to address the verification needs of AMD customers.

Vivado Simulator is a hardware description language (HDL) event-driven simulator that supports behavioral and timing simulation for single language and mixed language designs.

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AMD Vivado Simulator

  • Key Features

    Language Support
    • SystemVerilog (Including constraint randomization and functional coverage)
    • Verilog 2001
    • VHDL 93 and VHDL 2008
    Debugging and Verification
    • Advanced waveform viewer that supports digital/analog waveform & transaction view
    • Comprehensive debugging tools such as breakpoints, subprogram debug and cross-probing
    • Support for UVM 1.2 library
    • Functional Coverage
    • Support both GUI and script mode
    Co-simulation
    • Direct programming interface (DPI)
    • Xilinx simulation interface (XSI)

Support & Resources