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  3. SHA-3 Hash Crypto Engine

SHA-3 Hash Crypto Engine

  • Part Number: SHA3-B219
  • Vendor: BERTEN DSP S.L.
  • Partner Tier: Elite Certified
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Product Description

The SHA3-B219 is a crypto IP Core for hardware offloading of Hash algorithms. The engine implements the Secure Hash Algorithm 3 (SHA-3) family according to FIPS-202 standard. It includes fixed-length (SHA3-224, SHA3-256, SHA3-384, SHA3-512) and extendable-output functions (SHAKE128, SHAKE256). It also supports the KMAC (KECCAK Message Authentication Code) operation according to NIST 800-185.

SHA3-B219 implements the KECCAK sponge construction, including the insertion of the domain separation suffix, message padding, and data permutation functions.

With the context switching functionality, the internal state of the KECCAK engine can be saved and restored as needed to process other data.

Key Features and Benefits

  • AMBA AXI Interfaces
  • Portable to any FPGA or ASIC
  • FIPS 202 Compliant
  • Extendable-Output Functions (SHAKE128, SHAKE256)
  • Cryptographic Hashing (SHA3-224, SHA3-256, SHA3-384, SHA3-512)

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU5P -2 Vivado ML 2021.1 1006 5178 1 0 0 0 450
Kintex-UP Family XCKU5P -1 Vivado 2018.2 954 5228 1 0 0 0 405
Zynq-UP-MPSoC Family XCZU2CG -1 Vivado 2018.2 Y 934 5232 1 0 0 0 385
Spartan-7 Family XC7S50 -2 Vivado 2018.2 1560 5194 1 0 0 0 195
VERSAL_AI_CORE Family XCVC1802 -1 Vivado ML 2021.1 1041 4968 1 0 0 0 465
Artix-UP Family XCAU20P -2 Vivado ML 2021.2 1010 5179 1 0 0 0 485
KINTEX-7 Family XC7K70T -1 Vivado 2018.2 1546 5195 1 0 0 0 215
ARTIX-7 Family XC7A50T -2 Vivado 2018.2 1560 5194 1 0 0 0 195
VIRTEX-7X Family XC7VX550T -2 Vivado ML 2021.1 1610 5239 1 0 0 0 270
Zynq-7000 Family XC7Z030 -1 Vivado 2018.2 1543 5194 1 0 0 0 215
Zynq-7000 Family XC7Z020 -1 Vivado 2018.2 Y 1548 5195 1 0 0 0 155
VIRTEX-U Family XCVU080 -2 Vivado ML 2021.1 987 5176 1 0 0 0 380
KINTEX-U Family XCKU035 -1 Vivado 2018.2 931 5228 1 0 0 0 285

IP Quality Metrics

General Information

This Data was Current On Jun 06, 2024
Current IP Revision Number 2.1.294
Date Current Revision was Released Mar 16, 2023
Release Date of First Version Mar 03, 2022

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? Y
Driver OS Support Linux, Baremetal

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, UltraFast Design Methodology
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4-Stream
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology None
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Other

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Zedboard
Industry Standard Compliance Testing Passed N
Are Test Results Available? N