Product Description
DIFI is Geon Technologies’ Intellectual Property (IP) core for IEEE-ISTO Std 4900-2021 "Digital IF Interoperability Standard" compliant communications on a programmable logic device.
Key Features and Benefits
- Includes embedded C++ control/status software, C++ DIFI VITA49.2 packet software, and a Wireshark Plugin
- Includes reference project with an option of several AMD Zynq 7000 and Ultrascale+ development platforms
- Supports multiple streams of high or low-rate data for simultaneous transmit and receive
- Includes the full FPGA network stack to implement the DIFI standard
- Lead time is approximately 2 weeks
- Uses standard AXI4 buses
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-7000 Family | XC7Z030 | -1 | Vivado ML 2021.2 | Y | 29702 | 6896 | 46 | 0 | 0 | 4 | 250 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 07, 2024 |
| Current IP Revision Number | 0.0.01 |
| Date Current Revision was Released | Oct 10, 2022 |
| Release Date of First Version | Oct 10, 2022 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 2 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | Y |
| Model Formats | C++ |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | N |
| Driver OS Support | None |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | No |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | ZCU102 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |