AES-GCM: Authenticated Encryption/Description Core
- Part Number: AES-GCM
- Vendor: CAST, Inc.
- Partner Tier: Elite Certified
Product Description
The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths. Two architectural versions are available to suit system requirements. The Standard version (AES32) is more compact, using a 32-bit datapath and requiring 44/52/60 clock cycles for each data block (128/192/256-bit cipher key, respectively). The Fast version (AES128) achieves higher throughput, using a 128-bit datapath and requiring 11/13/15 clock cycles for each data block. GCM stands for Galois Counter. GCM is a generic authenticate-and-encrypt block cipher mode. A Galois Field (GF) multiplier/accumulator is utilized to generate an authentication tag while CTR (Counter) mode is used to encrypt.
Key Features and Benefits
- Standards: Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
- Size: From 778 ALMs to 5,812 ALMs depending on version and target device
- Configuration: Works with a pre-expended key or can integrate the optional key expansion function
- Deliverables: include test benches, C model and test vector generator
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Kintex-UP Family | XCKU11P | -1 | Vivado ML 2023.2 | 0 | 967 | 1 | 0 | 0 | 0 | 450 | |
| KINTEX-U Family | XCKU085 | -1 | Vivado ML 2023.2 | 0 | 876 | 1 | 0 | 0 | 0 | 275 | |
| VERSAL_PRIME Family | XCVM2902 | -1 | Vivado ML 2023.2 | 170 | 910 | 1 | 0 | 0 | 0 | 350 | |
| VIRTEX-7X Family | XC7VX330T | -3 | Vivado 2015.4 | 343 | 1062 | 0 | 0 | 0 | 0 | 300 |
IP Quality Metrics
General Information
| This Data was Current On | Sep 11, 2024 |
| Current IP Revision Number | 1.16 |
| Date Current Revision was Released | Jun 05, 2023 |
| Release Date of First Version | Oct 06, 2001 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 18 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | VHDL, Verilog |
| High-Level Model Included? | Y |
| Model Formats | C |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog, VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis; Mentor Precision; Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Synopsys VCS; Cadence NC-Sim; Mentor ModelSIM; Mentor Questa |
Hardware Validation
| Validated on FPGA | N |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |