Sony IMX Core
- Part Number: Sony IMX Core
- Vendor: Sensor to Image GmbH
- Partner Tier: Select Certified
Product Description
The IMX Pregius from Sony is a series of widely used, high quality CMOS image sensors. S2I’s IMX Pregius IP Core supports these sensors, it is able to read their data as well as controlling them. It is delivered as a reference design along with an FMC module compatible with S2I’s MVDK and standard FPGA evaluation kits. Together, they provide an easy way to design a camera.
Key Features and Benefits
- Core supports these sensors: Type A: IMX174, 249; Type B: IMX250, 252, 253, 255, 264, 265, 267; Type C: IMX273; Type D: IMX287, IMX174, IMX249, IMX302, IMX252, IMX265, IMX250, IMX264, IMX255, IMX267, IMX305, IMX253, IMX304, IMX273, IMX296, IMX297
- 4 function blocks: C library to write and read the sensor registers; physical FPGA interface to sensor control registers; FPGA based timing circuit to be connected to the sensor; FPGA based Sub-LVDS sensor readout
- CameraLink-Like output interface to connect easy to other streaming video IP
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ARTIX-7 Family | XC7A200T | -2 | Vivado 2019.1 | Y | 0 | 3488 | 1 | 0 | 1 | 0 | 150 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 2.1 |
| Date Current Revision was Released | Mar 16, 2023 |
| Release Date of First Version | Apr 24, 2016 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 15 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Source Code |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Artix-7 |
| Software Drivers Provided? | Y |
| Driver OS Support | n/a |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis / 2019.1 |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Code, Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Mentor ModelSIM / DE 6.5; Mentor ModelSIM / 10.x |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | AC701, KC705 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |