Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The AXI High Bandwidth Internal Configuration Access Port (HBICAP) LogiCORE™ IP core for the AXI Interface enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the internal configuration access port (ICAPEn).
The AXI High Bandwidth Internal Configuration Access Port (HBICAP) LogiCORE™ IP core for the AXI Interface enables an embedded microprocessor, such as the MicroBlaze™ processor, to read and write the FPGA configuration memory through the internal configuration access port (ICAPEn). This enables you to write software programs that modify the circuit structure and functionality during the operation of the circuit.
Note: The ICAPE2 primitive is applicable for 7 series devices. The ICAPE3 primitive is applicable forUltraScale™ and UltraScale+™ devices.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.