Product Description
The AXI VIP can be used to verify connectivity and basic functionality of AXI masters and AXI slaves with the custom RTL design flow. It also supports Passthrough mode which transparently allows the user to monitor transaction information/throughput or drive active stimulus. The AXI VIP provides example test benches and tests that demonstrate the abilities of AXI3, AXI4, and AXI4-Lite. These examples can be used as a starting point to create tests for custom RTL design with AXI3, AXI4, and AXI4-Lite interface. The examples can be accessed from IP Integrator.
There are no licenses required for use of AXI Verification IP.
Key Features and Benefits
- Supports all protocol data widths and address widths, transfer types and responses
- Full AXI Protocol Checker support
- Integrated ARM Licensed Protocol Assertions
- Transaction level protocol checking (burst type, length, size, lock type, cache type)
- Behavioral SystemVerilog Syntax
- SystemVerilog class-based API
- Configurable simulation messaging
- Delivered in Vivado Design Suite
- SystemVerilog example designs and test benches delivered in IP Integrator
- Supported Simulators: Aldec Riviera-PRO, Cadence Incisive Enterprise Simulator, Vivado Simulator, Mentor Graphics Questa Prime and Synopsys VCS
Support
Design Tools:
Featured Documents
- AXI Basics 1 - Introduction to AXI
- AXI Basics 2 - Simulating AXI interfaces with the AXI Verification IP (AXI VIP)
- AXI Basics 3 - Master AXI4-Lite simulation with the AXI VIP
- AXI Basics 4 - Using the AXI VIP as protocol checker for an AXI4 Master interface
- AXI Basics 5 - Create an AXI4-Lite Sniffer IP to use in Xilinx Vivado IP Integrator
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