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AXI Virtual FIFO Controller

The AXI Virtual FIFO Controller is a key interconnect infrastructure IP which enables users to access external memory segments as multiple FIFO blocks. The AXI Virtual Controller provides AMBA® AXI4-Stream write (master) as well as read (slave) interface to AXI4 DRAM memory mapped interface of external memory.

Design Tools Support: Vivado Software, ISE Design Suite
Bundled With: Vivado Software, ISE Design Suite
License: Core License Agreement
Device Support: Artix 7, Kintex 7, Kintex UltraScale+, Virtex 7, Virtex UltraScale+, Zynq 7000, Zynq UltraScale+ MPSoC

Overview
Documentation
Supported Tool Versions

Product Description

The AXI Virtual controller is provided under the terms of the End User License and is included with ISE™ and Vivado™ design tools at no additional charge.

AMD provides the AXI Virtual FIFO Controller core to use external DRAM memory as multiple FIFO blocks.

Key Features and Benefits

Configurable multiple FIFO interfaces (up to 8) channels.
FIFO FIFO full and empty check per channel
Supports data width of 32, 64, 128, 256, 512 and 1024.
Supports AXI4 memory mapped burst of 512, 1024, 2048 and 4096 bytes

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

PG038 - AXI Virtual FIFO Controller v2.0 Product Guide (PG038) (v2.0)

The AMD LogiCORE™ IP AXI Virtual FIFO Controller core (VFIFO) is a high performance core that implements multiple AXI4-Stream FIFOs.

View Release Note