Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
This IP is a 32-bit slave peripheral with an AXI4-Lite interface which provides the controller interface for the XADC hard macro on the Virtex™ 7, Kintex™ 7 families.
AXI XADC IP provides the controller interface for System Monitor XADC hard macro on the Virtex™ 7, Kintex™ 7, Artix™ 7 FPGA families and Zynq™ 7000 devices. This IP is a 32-bit slave peripheral with an AXI4-Lite interface which provides the controller interface for the XADC hard macro on the Virtex 7, Kintex 7, Artix 7 FPGA families and Zynq 7000 devices. It supports on-chip monitoring of supply voltages and temperature. This IP supports one dedicated high bandwidth differential analog-input pair and 16 auxiliary low bandwidth differential analog-input pairs.
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