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ChipScope™ Pro IBERT for Spartan™ 6 GTP Transceivers

Design Tools Support: ISE Design Suite
Bundled With: ISE Design Suite
License: End User License Agreement
Device Support: Spartan 6

Overview
Documentation

Product Description

The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for the Spartan™ 6 GTP transceiver is a customizable core that can be used to evaluate and monitor the health of the Spartan 6 GTP transceivers. The design includes pattern generators and checkers implemented in Field Programmable Gate Array (FPGA) logic, as well as access to the ports and dynamic reconfiguration port (Dynamic Reconfiguration Port) DPR attributes of the serial transceivers. Communication logic is also included and allows the design to be run-time accessible through Joint Test Action Group (JTAG). The IBERT core is a self-contained design, and when generated, runs through the entire implementation flow, including bit stream generation.

Key Features and Benefits

Provides a communication path between the ChipScope Pro Analyzer software and the IBERT core
Has user-selectable number of Spartan 6 GTP Transceivers
Each transceiver can be customized for the desired line rate, reference clock rate, reference clock source, and data path width
Requires a system clock that can be sourced from a pin or one of the enabled serial transceivers

Documentation

ISE Release Notes

This document contains a listing of release note tables, one for each IP core.

View Release Note

DS782 - ChipScope Integrated Bit Error Ratio Test (IBERT) for Spartan 6 GTP Data Sheet (DS782)

The AMD ChipScope™ Pro IBERT core for Spartan™ 6 GTP transceivers is customizable and can be used to evaluate and monitor Spartan 6 GTP transceivers.

View Data Sheet

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ChipScope™ Pro IBERT for Spartan™ 6 GTP Transceivers

Product Description

Key Features and Benefits

Related Products

ISE Release Notes

DS782 - ChipScope Integrated Bit Error Ratio Test (IBERT) for Spartan 6 GTP Data Sheet (DS782)

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