Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The Versal™ adaptive SoC DMA and Bridge Subsystem for PCIe provides a rich set of options for high performance data transfer between a Versal adaptive SoC and other devices using the widely deployed and industry standard PCI Express system architecture.
The Versal™ adaptive SoC DMA and Bridge Subsystem for PCIe provides a rich set of options for high performance data transfer between a Versal adaptive SoC and other devices using the widely deployed and industry standard PCI Express® system architecture. This subsystem is implemented within the robust and flexible Versal adaptive SoC integrated block for PCI Express with DMA and cache coherent interconnect (CPM4 or CPM5). Three functional modes are available:
QDMA Functional Mode:
AXI Bridge Functional Mode:
XDMA Functional Mode (CPM4 only):
Maximum supported link rates and widths with CPM5:
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.