ISE Release Notes
This document contains a listing of release note tables, one for each IP core.
by: AMD
The Digital Clock Manager (DCM) primitive in AMD FPGA parts is used to implement delay locked loop, digital frequency synthesizer, digital phase shifter, or a digital spread spectrum.
The Digital Clock Manager (DCM) primitive in AMD FPGA parts is used to implement delay locked loop, digital frequency synthesizer, digital phase shifter, or a digital spread spectrum. The digital clock manager module is a wrapper around the DCM primitive which allows it to be used in the EDK™ tool suite.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.