64-bit Initiator/Target for PCI-X & 32- and 64-bit Initiator/Target for PCI
- Part Number:
- EF-DI-PCIX64-VE-SITE
Product Description
DO-DI-PCIX64-VE rolls the Initiator/Target for PCI™/PCI-X™, 32-bit Initiator/Target for PCI and 64-bit Initiator/Target for PCI LogiCORE™ IP cores into one convenient product bundle.
The Initiator/Target for PCI™/PCI-X™ supports the PCI-X v2.0 mode 1 specification and can provide accelerated time-to-market advantage for designers of high throughput communications systems. AMD provides a netlist of the Initiator/Target PCI-X solution for 64-bit designs running at speeds of up to 133 MHz. The 32-bit and 64-bit Initiator/Target for PCI cores enable designers to build a customized PCI solution running at speeds up to 66 MHz.
The DO-DI-PCI-VE product bundle includes the following PCI and PCI-X core configurations
| DO-DI-PCI-VE PCI Configurations | |||
| FPGA Device | Performance | IP Overviews | Technical Documents |
| Kintex™ 7, Artix™ 7, Zynq™ 7000, Virtex™ 5, Virtex 4, Virtex II Pro, Spartan™ 6 (33 Mhz only), Spartan 3 generation | 64-bit 66 MHz |
Standalone | Data sheet |
| Kintex 7, Artix 7, Zynq 7000, Virtex 5, Virtex 4, Virtex II Pro, Spartan 6 (33 Mhz only), Spartan 3 generation | 32-bit 66 MHz |
Standalone | Data sheet |
| Virtex 4, Virtex II Pro, Spartan 3 generation | 32-bit 66 MHz or 33 MHz |
OPB/PLB* | Data sheet |
| Virtex 5, Virtex 4, Spartan 3 generation | 32-bit 33 MHz |
PLB v4.6* | Data sheet |
| DO-DI-PCI-VE PCI-X Configurations | |||
| FPGA Device | Performance | IP | Technical Documents |
| Virtex 5, Virtex 4, Virtex II Pro | 64-bit 133 MHz |
Data sheet | |
Please refer to the individual data sheet for each core for part and package support information. To generate the Core Generator license key for the respective product, please link to the IP Overview page and select access lounge on the left hand side.
Key Features and Benefits
- Fully PCI-X 2.0 Mode1 compliant core, 64-bit, 133/66MHz interface with 3.3 V operation
- Customizable, programmable, single-chip solution
- Predefined implementation for predictable timing
- Incorporates Smart-IP™ Technology
- Fully PCI 3.0 core compliant, 64/32-bit, 33 MHz PCI initiator and target interface
- 3.3v PCI-X operation at 33-133 MHz, 3.3V PCI operation at 0-33 MHz
- Fully verified design tested with Xilinx proprietary testbench
- Optional dual-port FIFOs may be added for maximum burst performance
- Integrated extended capabilities - PCI-X Capability Item, Power Management Capability Item, Message Signalled Interrupt Capability Item
- Available for configuration and download on the web