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100G IEEE 802.3bj and IEEE 802.3ck Reed-Solomon Forward Error Correction

AMD offers the 100G IEEE 802.3bj and IEEE 802.3ck Reed-Solomon Forward Error Correction (RS-FEC) IP core for high performance applications. This core is designed to the IEEE 802.3bj-2014 section 91.

Part Number:
- EF-DI-100G-RS-FEC-SITE
- EF-DI-100G-RS-FEC-PROJ
Design Tools Support: Vivado Software
License: Core License Agreement
Device Support: Kintex UltraScale+, Zynq UltraScale+ MPSoC, Versal Prime, Versal AI Core, Virtex UltraScale, Virtex UltraScale+

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Overview
Documentation
Supported Tool Versions

Product Description

AMD offers the 100 Gigabit IEEE 802.3bj and IEEE 802.3ck Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications. This core is designed to the IEEE 802.3bj-2014 and IEEE 802.3ck-2022 specification and connects seamlessly to the AMD integrated or soft 100G Ethernet MAC IP on Versal™ or UltraScale™ families.

Key Features and Benefits

Supports RS(528,514) KR4, RS(544,514) KP4, and 802.3ck RS(544, 514)
Low latency
Supports 100 Gigabits
Configuration and status bus
Selectable AXI4-Lite interface for status output
Transcode Bypass mode for direct access to RS-FEC encoder/decoder
Example reference design demonstrating integrated 100G Ethernet IP with RS-FEC
ECC RAM option

Resource Utilization

IEEE 802.3bj 100G RS-FEC Resource Utilization (Registration Required)

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

IEEE 802.3bj RS-FEC Product Guide

Registration Required.

View Product Guide

PB028 - 100G IEEE 802.3bj/ck Reed-Solomon FEC 100G IEEE802.3bj/ck RS-FEC v2.0 (PB028) (v2.0)

Implements the RS-FEC sublayer as described in IEEE 802.3bj-2014, section 91 and IEEE 802.3ck-2022, section 161.

View Product Brief