ERNIC

The ERNIC (Embedded RDMA enabled NIC) Core IP targets embedded application system which requires RDMA over Converged Ethernet (RoCE v2) for high throughput and low latency transmission over Ethernet networks. The most ideal use case is to deploy ERNIC Core IP in a FPGA to capture large number of sensors, videos, images and/or data stream, and send back to Host side for further processing.

The ERNIC Core includes a Queue Manager, Response Handler, Receiver (Rx) packet handler and Transmitter (Tx). The ERNIC Core IP provides AXI interface to work with wide variety of AMD hard and soft MAC IP.

The ERNIC Core IP allows simultaneous connections to multiple remote hosts running RoCE v2 traffic.

ERNIC Core IP block diagram

An ERNIC Example Design1 will be provided as reference to start a ERNIC Core IP design in a Versal or Ultrascale+ FPGA. The ERNIC Example Design includes a packet filter to separate RoCE v2 vs non-RoCE V2 traffic. The example design shows a typical RDMA target side implementation where the receiver and transmitter data paths connect to FPGA’s NoC, DDR memory controller and programmable logic. An embedded Linux driver is also provided as part of example design to allow FPGA’s PS (Processing System) to initiate, configure and manage RDMA connections.

Note 1 : Requires an ERNIC IP license.