Product Description
The Finite Impulse Response (FIR) Filter is one of the most ubiquitous and fundamental building blocks in DSP systems. Although its algorithm is extremely simple, the variants on the implementation specifics can be immense and a large time sink for hardware engineers today, especially in filter-dominated systems like Digital Radios.The FIR Compiler reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware architectures of their FIR Filter specification.
Key Features and Benefits
- Delivers VHDL demonstration testbench with CORE Generator
- Supports Pipelined Direct-Form based Multiply Accumulate (MAC) FIR and Transposed Direct-Form based MACFIR
- High-performance finite impulse response (FIR), polyphase decimator, polyphase interpolator, half-band, half-band decimator and half-band interpolator, Hilbert transform, and interpolated filter implementations
- Advanced interleaved channels to enable implementation of configurable bandwidth feature for advanced systems
- Multi-column support of DSP48/DSP58 slices for symmetric filter implementations
- A fixed point bit-accurate C-Model to enable system level analysis of Xilinx FIR Compiler core
- Multiple implementation architectures: DAFIR, Adder Tree based MACFIR (suitable for Mult18x18 enabled devices) and Adder Chain based MACFIR (suitable for XtremeDSP™ slice enabled devices)
- Performance reaching up to 680 MHz for Versal devices (-1LP speed grade)
- Supports 2 -2048 taps
- Automatic control of hardware folding for the most compact implementation
- Support for up to 64 channels (Channel = independent stream of voice / data / video, uncorrelated to other such streams that the FPGA is concurrently processing.
- Interpolation and decimation factors of up to 64 generally and up to 1024 for single channel filters
- Support for Reloadable Coefficients and up to 16 coefficient sets
- Automatic Coefficient structure optimizations to reduce area consumed: Symmetry and Halfband
- Automatic selection of Block vs Distributed Memory for Data and Coefficient storage
- For use with Vivado™ IP Integrator, Vivado IP Catalog and AMD System Generator for DSP™
- Support for super sample rate filter configurations
- For use with Vivado IP Integrator, Vivado IP Catalog and Vitis Model Composer
Resource Utilization
Support
Design Tools:
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1. Choose your IP Solution
Choose the AMD FIR Compiler for applications that need a filter and a wide range of features. For more information refer to the FIR Compiler Product Page or to the Features section of the FIR Compiler Product Guide (PG149).
2. Configure the IP
Before configuring the FIR Compiler, use a Filter Design tool, such as MATLAB®, to generate coefficients for the application.
- Mathworks – coeffs() function
- Mathworks – Create a FIR Filter Using Integer Coefficients
Once you have the coefficients, configure the IP customization options. For details, the Customizing and Generating the Core section in the Design Flow Steps chapter of the FIR Compiler Product Guide (PG149).
Start by configuring the following options:
- Filter Options Tab:
- Filter Coefficients - Enter your coefficients generated in your Filter Design tool.
- Filter Specification - Select the Type of Filter Implementation.
- Channel Specification Tab:
- Hardware Oversampling Specification.
- Set the Input Sample Rate and the Clock Frequency.
- Summary Tab:
- Review the Summary of Configuration.
In addition, review the following tabs on the left side of the GUI:
- Freq. Response: This enables you to verify that the frequency response matches your filter design requirements.
- Implementation Details: This enables you to see the resources consumed by your filter configuration.
After the IP has been configured, generate the IP solution.
3. Generate the Example Design for a Demonstration Board
The FIR Compiler generates an example test bench along with the IP. Information on the test bench can be found in the Test Bench chapter of the FIR Compiler Product Guide (PG149). The best way to test a FIR Compiler implementation is to implement an impulse and review the impulse response in simulation. Many simulation tools allow formatting of the output in an analog format, which will give a visual view of the impulse response that can be reviewed in addition to the data response.
4. Integration
Now you are ready to integrate the FIR Compiler into your own application. The user interface is described in the Port Description section in the Product Specification chapter of the FIR Compiler Product Guide (PG149). Review the simulation in Step 3 as a reference on the expected waveforms for the interface ports.