This LDPC IP core consists of an LDPC encoder and FAID™ decoder achieving a maximum decoding throughput of 1.7Gbytes/s for NAND flash controllers supporting the next generation of NAND flash memories.
TCP/IP Full Accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.
UDP100G-IP is fully offload 100G UDP engine by pure hardware logic without CPU. Suitable for high performance and low latency applications such as data streaming and broadcasting over 100G network.
TOE100G-IP core is high performance, full TCP/IP stack implementation by pure hardwired logic without CPU.
Enabling 100G TCP transmission at maximum performance without bottleneck from Host systems.
UDP10G-IP is fully offload 10G UDP engine by pure hardware logic without CPU. Suitable for high performance and low latency applications such as data streaming and broadcasting over 10G network.
The 10G Ultra-Low Latency Ethernet MAC / PCS / PMA is the industry leading solution for latency critical Ethernet applications such as high-frequency trading and data center Ethernet switches.
TOE10G-IP core is high performance, full TCP/IP stack implementation by pure hardwired logic without CPU.
Enabling 10G TCP transmission at maximum performance without bottleneck from Host systems.
QUIC Client 10Gbps IP core (QUIC10GC-IP) is engineered from the ground up to simplify the QUIC protocol with TLS 1.3 security into pure hardware logic for FPGA-based client applications.
This IP core is bundle of 13 different SHA-3 competitor cryptographic hash functions originally submitted to NIST hash competition.All these cores are fully pipelined & deliver 35.7GBps throughput.
UDP1G-IP is fully offload 1G UDP engine by pure hardware logic without CPU. Suitable for high performance and low latency applications such as data streaming and broadcasting over 1G network.
The 25G EMAC/PCS + RS-FEC IP core provides a comprehensive implementation of the physical layer, including the Ethernet MAC layer, Physical Coding sublayer (PCS), and RS-FEC sublayer.
The 25G MAC/PCS core provides high performance connectivity to significantly increase the efficiency and rate of data transfer in Virtex UltraScale FPGAs.
UDP25G-IP is fully offload 25G UDP engine by pure hardware logic without CPU. Suitable for high performance and low latency applications such as data streaming and broadcasting over 25G network.
TOE25G-IP core is high performance, full TCP/IP stack implementation by pure hardwired logic without CPU.
Enabling 25G TCP transmission at maximum performance without bottleneck from Host systems.
UDP40G-IP is fully offload 40G UDP engine by pure hardware logic without CPU. Suitable for high performance and low latency applications such as data streaming and broadcasting over 40G network.
TOE40G-IP core is high performance, full TCP/IP stack implementation by pure hardwired logic without CPU.
Enabling 40G TCP transmission at maximum performance without bottleneck from Host systems.
This LDPC IP core consists of an LDPC encoder and FAID™ decoder achieving a maximum decoding throughput of 6.5Gbytes/s for NAND flash controllers supporting the next generation of NAND flash memories.
XIP3030C is a compact IP core with versatile support for all variants of the SHA-3 hash function SHA-3; SHAKE128/256, cSHAKE, KMAC, TupleHash and ParallelHash.
XIP3030H is a high-speed IP core with versatile support for all variants of the SHA-3 hash function SHA-3; SHAKE128/256, cSHAKE, KMAC, TupleHash and ParallelHash.