2. Intellectual Property
  3. DMA for PCI Express (PCIe) Subsystem

DMA for PCI Express (PCIe) Subsystem

Overview

Product Description

The AMD LogiCORE™ DMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express Integrated Block.  The IP provides an optional AXI4-MM or AXI4-Stream user interface.

Drivers

Reference drivers are available at https://github.com/Xilinx/dma_ip_drivers and https://www.xilinx.com/member/xdma_windows_driver.html

Key Features and Benefits

  • DMA for PCI Express Subsystem connects to the PCI Express Integrated Block. Both IPs are required to build the PCI Express DMA solution
  • Support for 64, 128, 256, 512-bit datapath for UltraScale+™, UltraScale™ devices.  Support for 64 and 128-bit datapath for Virtex™ 7 XT devices
  • Up to 4 host-to-card (H2C/Read) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex 7 XT devices
  • Up to 4 card-to-host (C2H/Write) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex 7 XT devices
  • 64-bit source, destination, and descriptor addresses
  • Per channel descriptor bypass for custom descriptor creation
  • Configurable user interface
    • Common AXI4 memory mapped (MM) user interface
    • A separate AXI4-Stream user interface
  • AXI Master interfaces enable PCIe reads and writes to bypass the DMA engine

Resource Utilization

Support

Device Family:

Design Tools:

Documentation

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