Thread Synthesis and Reordering attachment IP for use with random access masters to HBM IP
Product Description
For use with single-threaded, random access masters to improve overall HBM bandwidth
RAMA IP, made available for Virtex UltraScale+ HBM devices, attaches between an AXI fabric master and the HBM AXI slave infrastructure. It generates temporary IDs so that transactions with the same original ID may be reordered. This relieves congestion within the HBM switch and allows transactions to complete based on the native latency of the memory. Data is then coalesced within RAMA and returned in the order it was requested.
Included at no additional charge with Vivado software
Key Features and Benefits
- Thread Synthesis, allows instructions to complete out of order, relieving congestion in the HBM switch
- Coalesces sparse read data
- Acknowledges instructions and returns read data in the order in which they were received
- Supports the maximum transaction size, 512B
- Ideal for masters accessing more than one HBM Pseudo Channel
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