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Virtex™ 5 Embedded Tri-mode Ethernet MAC Wrapper

Design Tools Support: ISE Design Suite
Bundled With: ISE Design Suite
License: End User License Agreement
Device Support: Virtex 5

Overview
Documentation

Product Description

The CORE Generator™ Virtex™ 5 Embedded Tri-mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL wrapper files for the embedded Tri-mode Ethernet MAC in Virtex 5 devices. Preconfigured HDL wrappers as well as testbenches and implement and simulation scripts are generated automatically based on user defined options.

Key Features and Benefits

Provides user configurable Virtex 5 Tri-mode Ethernet MAC (TEMAC) physical interface
Simplifies interconnection between the Ethernet MAC and the PHY
Allows selection of one or both of the two Ethernet MACs (EMAC0 or EMAC1) from the Ethernet MAC primitive
Individual DCR base address for EMAC0/EMAC1
Sets EMAC0/EMAC1 attributes based on user options
Supports MII, GMII, RGMII v1.3, RGMII v2.0, SGMII, and 1000BASE-X PCS/PMA interfaces
Clock Enable inputs on the Transmit and Receive clients available when the Ethernet MAC is configured in GMII/MII or RGMII modes (halves the BUFG requirements)
"Byte PHY" clocking scheme for Tri-Mode GMII/MII (halves the BUFG requirements)
Instantiates BUFs, DCMs, GTPs, and logic required for MII, GMII, RGMII, SGMII, and 1000BASE-X PCS/PMA interfaces
Includes testbench for wrappers using the EMAC and GTP Smartmodels
Generates VHDL or Verilog® wrappers
16-bit client interface supports 2Gb/s data rates
Implementation scripts and UCF file
Simulation scripts for Mentor® Modelsim® and Cadence™ IUS (functional and timing simulation)

Documentation

ISE Release Notes

This document contains a listing of release note tables, one for each IP core.

View Release Note

DS550 - Virtex 5 Embedded Tri-Mode Ethernet MAC Wrapper v1.8 Data Sheet (DS550) (v1.8)

The LogiCORE™ IP Virtex™ 5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex 5 LXT, SXT, FXT and TXT FPGAs using the AMD CORE Generator™ software.

View Data Sheet

UG194 - Virtex 5 FPGA Embedded Tri-Mode Ethernet MAC User Guide (UG194) (v1.1)

Virtex 5 FPGA Embedded Tri-Mode Ethernet MAC User Guide

View User Guide

UG340 - Virtex 5 Embedded Tri-Mode Ethernet MAC Wrapper Getting Started Guide (UG340) (v1.8)

Automates the generation of HDL wrapper files for the Tri-Mode Ethernet MAC in Virtex 5 devices using the AMD CORE Generator.

View User Guide

_{Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.}

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Virtex™ 5 Embedded Tri-mode Ethernet MAC Wrapper

Product Description

Key Features and Benefits

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