Have You Considered a FPGA For Your Next Inverter Design?

As new power switching technologies, such as Gallium Nitride (GaN) and Silicon Carbide (SiC), begin to become mainstream in power electronics, many advantages over traditional Silicon IGBTs and MOSFETs begin to become apparent with respect to higher operating voltages, higher temperature, and higher switching frequencies.  Moreover, the insatiable need for data for optimizing battery life, providing data logging of all the motor’s electrical and mechanical variables for fleet optimization, and predicting possible mechanical and electrical failures, requires a control platform that exceeds what is available today in standard DSP and microcontrollers architectures. If you were a traction inverter designer for electric vehicles (EVs), questions may start to arise that keep you up at night! Can my DSP or microcontroller fully achieve the performance required for such challenges? Can the system benefit from these new power switching technologies?  Can my DSP manage these increases in computational demands and calculate its’ switching algorithm fast enough before the next interrupt hits, sending me into a catastrophic nested interrupt frenzy?  Setting aside various design aspects such as optimal bus bar design, thermal management, and proper isolation techniques, let us focus on computation aspects where Xilinx technology offers a paradigm shift on how these requirements and fast switching speeds can be realized.

For this article, let us consider a Xilinx Zynq System-on-Chip (SoC) in which a designer can take full advantage of the Programmable Logic (PL) within the device as well as the ARM cores in the Processing System (PS) and let us examine the classic Field Oriented Control (FOC) algorithm used for a 3-phase Voltage Source Inverter (VSI).

Taking the motor’s currents (and sometimes the motor’s voltages) as main feedback variables, while using torque (current) and flux as main control variables, we apply a set of transformations from three phases to two phases (Clarke transform), map these signals from this rotating frame into a fixed frame (Park transform) and with the help of a Proportional-Integral (PI) controller, torque and flux can thus be independently managed. All these transformations are simple matrix calculations.  By then using an inverse Park and inverse Clarke transformation a Space Vector Modulator PWM (SVMPWM) can be driven ultimately delivering the switching pulses to the power transistors.

 From a traditional computing approach implemented with a microcontroller or DSP, execution of these matrix operations would be done in a sequential fashion where each element of the array would be multiplied and then added to the next element per the definition of matrix mathematics. Traditionally the computation is executed within 50 µs (~20 kHz) but smaller motors can require a faster computation quickly putting you in the region of 10 µs or less!  Such timings are challenging if your algorithm must be executed as part of the interrupt service routine fighting with other resources shared on the microchip.  From a traditional computing aspect, the end result is that once your control algorithm has been developed, any changes in timing, an additional computational requirement that may arise for market reasons, or technical improvements, may result in needing to recalibrate the control software.

By contrast, a Xilinx System on Chip can use the programmable logic to implement the same algorithm, removing any direct computational dependency on the processors and, thus, leaving the processors to manage more control flow-intensive applications. The implementation in programmable logic is very simple and fully supported with Xilinx’s own open-source solution available on Xilinx’s Github Repository with documented C++ code and a getting started guide.  Xilinx’s High-Level Synthesis (HLS) compiler transforms your C/C++ Park, Clarke, PI, and SVMPWM into programmable hardware using a deterministic dataflow architecture where the next element of the array can begin to be computed while the current element’s computation is being finished, resulting in significant speed increases of your algorithm.  This faster computation can directly correlate to improved efficiency, smaller physical parts, and greater range for your EV.

It is also important to show a ‘model-based development approach where Xilinx provides Vitis Model Composer.  This tool allows the user to create custom hardware blocks that can be integrated into a MATLAB Simulink model and then compiled into the FPGA’s programmable logic.  Understand that these blocks are not merely auto-generating HDL but are highly optimized logic that can take advantage of complex DSP-slices within the FPGA without the hassle or worry of closing timing or optimizing routing.  It allows the user to quickly realize hardware acceleration within the FPGA while focusing on your problem.

As we start to understand the benefits that programmable logic can bring us in terms of pipelining and optimization of our computational algorithms, there are even more benefits that an FPGA-based design can bring you.

Figuring out the position of the rotor in reference to the stator can provide added benefits in how you control your motor.  Traditionally, this has been done with an external integrated circuit which adds cost to your design as well as accuracy.  Using an external ADC and DAC, one can come up with a simple PI-controller which replaces the resolver yet provides more accurate results.  The FPGA can control the DAC to generate a sine wave while the ADC samples the returned sine and cosine waveforms from the stator and thus use trigonometric relationships to determine the position of the motor.  As EV’s become more complex with dual and possibly four motors, the added cost of multiple resolver circuits can add up.  To compensate, multi-channel ADCs and DACs can be used, and resolver computation can be offloaded into the programmable logic of the FPGA.  This offload of computation can also include a digital filter where a filter implemented in the programmable logic can operate in the 100MHz range greatly reducing phase lag when compared to an external resolved or analog filter chain.  Overall, the added benefit to the do-it-yourself resolver is the accuracy in which external resolvers may often claim a ±10° window of accuracy while control within a FPGA have shown as little as a ±2° window of accuracy, thus allowing your solution to accurately manage torque and flux for better motor efficiency.

As if fasting switching frequencies was not enough of a challenge, it seems that the electronics world has seen a revolutionary shift to artificial intelligence for processing and understanding new possibilities on many classic problems.  Surely, you might ask, how can something so cutting-edge be applied to a simple motor control application?  Would you be surprised that neural networks have found their way to into algorithms for controlling optimal switching times for gate drivers?  Would you be surprised to find out that neural networks can be used for diagnostic and even prognostic scenarios to monitor motor health?  By using trained neural networks for such purposes, automotive makers can determine if a part is failing, alert a driver for preventative maintenance, and in a connected car world, extrapolate if batches or lots of a certain part to exhibit the same characteristics and thus understand why a part may be failing in a particular fashion.  It is important to note that Xilinx offers our Deep Learning Processor Unit (DPU) for Zynq-based devices which can get designers, unacquainted with the aspects of artificial intelligence, up and running in no time at all!

We have mentioned algorithm implementation and acceleration, development flows, and added benefits to using Xilinx Zynq based devices, but how do we bring these all together for our overall solution?  Xilinx’s Vivado provides a developer an easy-to-use experience where algorithms can be exported into Intellectual Property (IP) ‘blocks’ and connected together in our Intellectual Property Integrator (IPI) using these custom cores or instantiating ready-to-go logic.  For example, an encoder algorithm may be written purely in an HDL language, your FOC developed in Vitis Model Composer, a DPU taken off-the-shelf and instantiated into your design.  All of these can be tied together using the IPI composing programmable hardware alongside an AutoSAR stack independently running on the ARM cores in the processing system.

I hope that in reading this article you ask yourself not if you have considered an FPGA for your inverter design, but why haven’t you considered an FPGA for your inverter design.  Realizing faster algorithm calculations can get you to the switching speeds these new transistor technologies can provide along with added benefits that you may have not considered before. 

For more information, please contact paul.karatsinides@xilinx.com