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AI Engine-ML Intrinsics User Guide (v2024.2)
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Matrix multiplications in which matrix A has data elements of 32 bit and matrix B has data elements of 32 bit. These operations are emulated on top of Multiply-accumulate of 32b x 16b integer datatypes and Multiply-accumulate of 16b x 16b integer datatypes and might not have optimal performance. More...
Matrix multiplications in which matrix A has data elements of 32 bit and matrix B has data elements of 32 bit. These operations are emulated on top of Multiply-accumulate of 32b x 16b integer datatypes and Multiply-accumulate of 16b x 16b integer datatypes and might not have optimal performance.
For an explanation how these operations works see Multiply Accumulate.
Emulated Multiplication of (4x2) with (2x4) Matrices (32b * 32b) | |
v16acc64 | mul_4x2_2x4 (v16uint32 a, v16uint32 b0) |
v16acc64 | negmul_4x2_2x4 (v16uint32 a, v16uint32 b0) |
v16acc64 | mac_4x2_2x4 (v16uint32 a, v16uint32 b0, v16acc64 acc1) |
v16acc64 | msc_4x2_2x4 (v16uint32 a, v16uint32 b0, v16acc64 acc1) |
v16acc64 | mul_4x2_2x4 (v16uint32 a, v16int32 b0) |
v16acc64 | negmul_4x2_2x4 (v16uint32 a, v16int32 b0) |
v16acc64 | mac_4x2_2x4 (v16uint32 a, v16int32 b0, v16acc64 acc1) |
v16acc64 | msc_4x2_2x4 (v16uint32 a, v16int32 b0, v16acc64 acc1) |
v16acc64 | mul_4x2_2x4 (v16int32 a, v16uint32 b0) |
v16acc64 | negmul_4x2_2x4 (v16int32 a, v16uint32 b0) |
v16acc64 | mac_4x2_2x4 (v16int32 a, v16uint32 b0, v16acc64 acc1) |
v16acc64 | msc_4x2_2x4 (v16int32 a, v16uint32 b0, v16acc64 acc1) |
v16acc64 | mul_4x2_2x4 (v16int32 a, v16int32 b0) |
v16acc64 | negmul_4x2_2x4 (v16int32 a, v16int32 b0) |
v16acc64 | mac_4x2_2x4 (v16int32 a, v16int32 b0, v16acc64 acc1) |
v16acc64 | msc_4x2_2x4 (v16int32 a, v16int32 b0, v16acc64 acc1) |
Emulated Multiplication of (4x2) with (2x4) Matrices (32b * 32b) with dynamic sign | |
v16acc64 | mul_4x2_2x4 (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y) |
v16acc64 | negmul_4x2_2x4 (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y) |
v16acc64 | mac_4x2_2x4 (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1) |
v16acc64 | msc_4x2_2x4 (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1) |
v16acc64 | mul_4x2_2x4 (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y) |
v16acc64 | negmul_4x2_2x4 (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y) |
v16acc64 | mac_4x2_2x4 (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1) |
v16acc64 | msc_4x2_2x4 (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1) |
v16acc64 | mul_4x2_2x4 (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y) |
v16acc64 | negmul_4x2_2x4 (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y) |
v16acc64 | mac_4x2_2x4 (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1) |
v16acc64 | msc_4x2_2x4 (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1) |
v16acc64 | mul_4x2_2x4 (v16int32 a, int sgn_x, v16int32 b0, int sgn_y) |
v16acc64 | negmul_4x2_2x4 (v16int32 a, int sgn_x, v16int32 b0, int sgn_y) |
v16acc64 | mac_4x2_2x4 (v16int32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1) |
v16acc64 | msc_4x2_2x4 (v16int32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1) |
Emulated Multiplication of (4x2) with (2x4) Matrices (32b * 32b) with dynamic negation of multiplication result | |
v16acc64 | mul_4x2_2x4_conf (v16uint32 a, v16uint32 b0, int sub_mul) |
v16acc64 | negmul_4x2_2x4_conf (v16uint32 a, v16uint32 b0, int sub_mul) |
v16acc64 | mul_4x2_2x4_conf (v16uint32 a, v16int32 b0, int sub_mul) |
v16acc64 | negmul_4x2_2x4_conf (v16uint32 a, v16int32 b0, int sub_mul) |
v16acc64 | mul_4x2_2x4_conf (v16int32 a, v16uint32 b0, int sub_mul) |
v16acc64 | negmul_4x2_2x4_conf (v16int32 a, v16uint32 b0, int sub_mul) |
v16acc64 | mul_4x2_2x4_conf (v16int32 a, v16int32 b0, int sub_mul) |
v16acc64 | negmul_4x2_2x4_conf (v16int32 a, v16int32 b0, int sub_mul) |
Emulated Multiplication of (4x2) with (2x4) Matrices (32b * 32b) with dynamic negation of multiplication result, negation of acc1 | |
v16acc64 | mac_4x2_2x4_conf (v16uint32 a, v16uint32 b0, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16uint32 a, v16uint32 b0, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_4x2_2x4_conf (v16uint32 a, v16int32 b0, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16uint32 a, v16int32 b0, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_4x2_2x4_conf (v16int32 a, v16uint32 b0, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16int32 a, v16uint32 b0, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_4x2_2x4_conf (v16int32 a, v16int32 b0, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16int32 a, v16int32 b0, v16acc64 acc1, int sub_mul, int sub_acc1) |
Emulated Multiplication of (4x2) with (2x4) Matrices (32b * 32b) with dynamic sign and dynamic negation of multiplication result | |
v16acc64 | mul_4x2_2x4_conf (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y, int sub_mul) |
v16acc64 | negmul_4x2_2x4_conf (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y, int sub_mul) |
v16acc64 | mac_4x2_2x4_conf (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mul_4x2_2x4_conf (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y, int sub_mul) |
v16acc64 | negmul_4x2_2x4_conf (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y, int sub_mul) |
v16acc64 | mac_4x2_2x4_conf (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mul_4x2_2x4_conf (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y, int sub_mul) |
v16acc64 | negmul_4x2_2x4_conf (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y, int sub_mul) |
v16acc64 | mac_4x2_2x4_conf (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mul_4x2_2x4_conf (v16int32 a, int sgn_x, v16int32 b0, int sgn_y, int sub_mul) |
v16acc64 | negmul_4x2_2x4_conf (v16int32 a, int sgn_x, v16int32 b0, int sgn_y, int sub_mul) |
v16acc64 | mac_4x2_2x4_conf (v16int32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16int32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
Emulated Multiplication of (4x2) with (2x4) Matrices (32b * 32b) with dynamic negation of multiplication result, negation of acc1 and zeroing of acc1 | |
v16acc64 | mac_4x2_2x4_conf (v16uint32 a, v16uint32 b0, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16uint32 a, v16uint32 b0, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_4x2_2x4_conf (v16uint32 a, v16int32 b0, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16uint32 a, v16int32 b0, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_4x2_2x4_conf (v16int32 a, v16uint32 b0, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16int32 a, v16uint32 b0, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_4x2_2x4_conf (v16int32 a, v16int32 b0, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16int32 a, v16int32 b0, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
Emulated Multiplication of (4x2) with (2x4) Matrices (32b * 32b) with dynamic sign and dynamic negation of multiplication result and zeroing of acc1 | |
v16acc64 | mac_4x2_2x4_conf (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16uint32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_4x2_2x4_conf (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16uint32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_4x2_2x4_conf (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16int32 a, int sgn_x, v16uint32 b0, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_4x2_2x4_conf (v16int32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_4x2_2x4_conf (v16int32 a, int sgn_x, v16int32 b0, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
Emulated Channel by channel multiplication of (1x2) with (2x1) (32b * 32b) with dynamic negation of multiplication result | |
v16acc64 | mul_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16uint32 b0, v16uint32 b1, int sub_mul) |
v16acc64 | negmul_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16uint32 b0, v16uint32 b1, int sub_mul) |
v16acc64 | mul_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16int32 b0, v16int32 b1, int sub_mul) |
v16acc64 | negmul_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16int32 b0, v16int32 b1, int sub_mul) |
v16acc64 | mul_elem_16_2_conf (v16int32 a0, v16int32 a1, v16uint32 b0, v16uint32 b1, int sub_mul) |
v16acc64 | negmul_elem_16_2_conf (v16int32 a0, v16int32 a1, v16uint32 b0, v16uint32 b1, int sub_mul) |
v16acc64 | mul_elem_16_2_conf (v16int32 a0, v16int32 a1, v16int32 b0, v16int32 b1, int sub_mul) |
v16acc64 | negmul_elem_16_2_conf (v16int32 a0, v16int32 a1, v16int32 b0, v16int32 b1, int sub_mul) |
Emulated Channel by channel multiplication of (1x2) with (2x1) (32b * 32b) with dynamic negation of multiplication result, negation of acc1 | |
v16acc64 | mac_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16uint32 b0, v16uint32 b1, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16uint32 b0, v16uint32 b1, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16int32 b0, v16int32 b1, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16int32 b0, v16int32 b1, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_elem_16_2_conf (v16int32 a0, v16int32 a1, v16uint32 b0, v16uint32 b1, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16int32 a0, v16int32 a1, v16uint32 b0, v16uint32 b1, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_elem_16_2_conf (v16int32 a0, v16int32 a1, v16int32 b0, v16int32 b1, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16int32 a0, v16int32 a1, v16int32 b0, v16int32 b1, v16acc64 acc1, int sub_mul, int sub_acc1) |
Emulated Channel by channel multiplication of (1x2) with (2x1) (32b * 32b) with dynamic sign and dynamic negation of multiplication result | |
v16acc64 | mul_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, int sub_mul) |
v16acc64 | negmul_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, int sub_mul) |
v16acc64 | mac_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mul_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, int sub_mul) |
v16acc64 | negmul_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, int sub_mul) |
v16acc64 | mac_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mul_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, int sub_mul) |
v16acc64 | negmul_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, int sub_mul) |
v16acc64 | mac_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | mul_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, int sub_mul) |
v16acc64 | negmul_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, int sub_mul) |
v16acc64 | mac_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, v16acc64 acc1, int sub_mul, int sub_acc1) |
Emulated Channel by channel multiplication of (1x2) with (2x1) (32b * 32b) with dynamic negation of multiplication result, negation of acc1 and zeroing of acc1 | |
v16acc64 | mac_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16uint32 b0, v16uint32 b1, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16uint32 b0, v16uint32 b1, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16int32 b0, v16int32 b1, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16uint32 a0, v16uint32 a1, v16int32 b0, v16int32 b1, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_elem_16_2_conf (v16int32 a0, v16int32 a1, v16uint32 b0, v16uint32 b1, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16int32 a0, v16int32 a1, v16uint32 b0, v16uint32 b1, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_elem_16_2_conf (v16int32 a0, v16int32 a1, v16int32 b0, v16int32 b1, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16int32 a0, v16int32 a1, v16int32 b0, v16int32 b1, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
Emulated Channel by channel multiplication of (1x2) with (2x1) (32b * 32b) with dynamic sign, zeroing of acc1 and dynamic negation of multiplication result | |
v16acc64 | mac_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16uint32 a0, v16uint32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16uint32 b0, v16uint32 b1, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | mac_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
v16acc64 | msc_elem_16_2_conf (v16int32 a0, v16int32 a1, int sgn_x, v16int32 b0, v16int32 b1, int sgn_y, v16acc64 acc1, int zero_acc1, int sub_mul, int sub_acc1) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
v16acc64 mac_4x2_2x4_conf | ( | v16int32 | a, |
int | sgn_x, | ||
v16int32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16int32 | a, |
int | sgn_x, | ||
v16int32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16int32 | a, |
int | sgn_x, | ||
v16uint32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16int32 | a, |
int | sgn_x, | ||
v16uint32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16int32 | a, |
v16int32 | b0, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16int32 | a, |
v16uint32 | b0, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16uint32 | a, |
int | sgn_x, | ||
v16int32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16uint32 | a, |
int | sgn_x, | ||
v16int32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16uint32 | a, |
int | sgn_x, | ||
v16uint32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16uint32 | a, |
int | sgn_x, | ||
v16uint32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16uint32 | a, |
v16int32 | b0, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_4x2_2x4_conf | ( | v16uint32 | a, |
v16uint32 | b0, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2 | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
v16acc64 mac_elem_16_2 | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
v16acc64 mac_elem_16_2 | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
v16acc64 mac_elem_16_2 | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
v16acc64 mac_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 mac_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
v16acc64 msc_4x2_2x4_conf | ( | v16int32 | a, |
int | sgn_x, | ||
v16int32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_4x2_2x4_conf | ( | v16int32 | a, |
int | sgn_x, | ||
v16int32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_4x2_2x4_conf | ( | v16int32 | a, |
int | sgn_x, | ||
v16uint32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_4x2_2x4_conf | ( | v16int32 | a, |
int | sgn_x, | ||
v16uint32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_4x2_2x4_conf | ( | v16int32 | a, |
v16int32 | b0, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_4x2_2x4_conf | ( | v16int32 | a, |
v16uint32 | b0, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_4x2_2x4_conf | ( | v16uint32 | a, |
int | sgn_x, | ||
v16int32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_4x2_2x4_conf | ( | v16uint32 | a, |
int | sgn_x, | ||
v16int32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_4x2_2x4_conf | ( | v16uint32 | a, |
int | sgn_x, | ||
v16uint32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_4x2_2x4_conf | ( | v16uint32 | a, |
int | sgn_x, | ||
v16uint32 | b0, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_4x2_2x4_conf | ( | v16uint32 | a, |
v16int32 | b0, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_4x2_2x4_conf | ( | v16uint32 | a, |
v16uint32 | b0, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a | Matrix A |
b0 | Matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask of acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_elem_16_2 | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
v16acc64 msc_elem_16_2 | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
v16acc64 msc_elem_16_2 | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
v16acc64 msc_elem_16_2 | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
v16acc64 msc_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
sub_acc1 | Negation mask of acc1. If a bit is set the corresponding accumulator lane of acc1 is negated. |
v16acc64 msc_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
v16acc64 | acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
v16acc64 msc_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
v16acc64 | acc1, | ||
int | zero_acc1, | ||
int | sub_mul, | ||
int | sub_acc1 | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
acc1 | Accumulator 1 input |
zero_acc1 | Zeroing mask for acc1 |
sub_mul | Negation mask of multiplication result |
sub_acc1 | Negation mask of acc1 |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
a | Matrix A |
b0 | Matrix B |
a | Matrix A |
b0 | Matrix B |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
a | Matrix A |
b0 | Matrix B |
a | Matrix A |
b0 | Matrix B |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
a | Matrix A |
b0 | Matrix B |
sub_mul | Negation mask for multiplication result |
a | Matrix A |
b0 | Matrix B |
sub_mul | Negation mask for multiplication result |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
a | Matrix A |
b0 | Matrix B |
sub_mul | Negation mask for multiplication result |
a | Matrix A |
b0 | Matrix B |
sub_mul | Negation mask for multiplication result |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
v16acc64 mul_elem_16_2 | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
a0 | Matrix A (first halft) |
a1 | Matrix A (second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
a0 | Matrix A (first halft) |
a1 | Matrix A (second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
v16acc64 mul_elem_16_2 | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
v16acc64 mul_elem_16_2 | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
a0 | Matrix A (first halft) |
a1 | Matrix A (second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
a0 | Matrix A (first halft) |
a1 | Matrix A (second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
v16acc64 mul_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
v16acc64 mul_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sub_mul | Negation mask for multiplication result |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sub_mul | Negation mask for multiplication result |
v16acc64 mul_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
v16acc64 mul_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result. If a bit is set the corresponding output accumulator lane is negated. |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sub_mul | Negation mask for multiplication result |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sub_mul | Negation mask for multiplication result |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
a | Matrix A |
b0 | Matrix B |
a | Matrix A |
b0 | Matrix B |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
a | Matrix A |
b0 | Matrix B |
a | Matrix A |
b0 | Matrix B |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result |
a | Matrix A |
b0 | Matrix B |
sub_mul | Negation mask for multiplication result. If a bit of sub_mul is set the corresponding vector lane of the output accumulator will be negated. |
a | Matrix A |
b0 | Matrix B |
sub_mul | Negation mask for multiplication result. If a bit of sub_mul is set the corresponding vector lane of the output accumulator will be negated. |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result |
a | Matrix A |
sgn_x | Sign mask for matrix A |
b0 | Matrix B |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result |
a | Matrix A |
b0 | Matrix B |
sub_mul | Negation mask for multiplication result. If a bit of sub_mul is set the corresponding vector lane of the output accumulator will be negated. |
a | Matrix A |
b0 | Matrix B |
sub_mul | Negation mask for multiplication result. If a bit of sub_mul is set the corresponding vector lane of the output accumulator will be negated. |
v16acc64 negmul_elem_16_2 | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
v16acc64 negmul_elem_16_2 | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
v16acc64 negmul_elem_16_2 | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
v16acc64 negmul_elem_16_2 | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
v16acc64 negmul_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result |
v16acc64 negmul_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sub_mul | Negation mask for multiplication result. If a bit of sub_mul is set the corresponding vector lane of the output accumulator will be negated. |
v16acc64 negmul_elem_16_2_conf | ( | v16int32 | a0, |
v16int32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sub_mul | Negation mask for multiplication result. If a bit of sub_mul is set the corresponding vector lane of the output accumulator will be negated. |
v16acc64 negmul_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sgn_y, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result |
v16acc64 negmul_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
int | sgn_x, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sgn_y, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
sgn_x | Sign mask for matrix A |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sgn_y | Sign mask for matrix B |
sub_mul | Negation mask of multiplication result |
v16acc64 negmul_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16int32 | b0, | ||
v16int32 | b1, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sub_mul | Negation mask for multiplication result. If a bit of sub_mul is set the corresponding vector lane of the output accumulator will be negated. |
v16acc64 negmul_elem_16_2_conf | ( | v16uint32 | a0, |
v16uint32 | a1, | ||
v16uint32 | b0, | ||
v16uint32 | b1, | ||
int | sub_mul | ||
) |
a0 | Matrix A (first halft) |
a1 | Matrix A (Second halft) |
b0 | Matrix B (first halft) |
b1 | Matrix B (second halft) |
sub_mul | Negation mask for multiplication result. If a bit of sub_mul is set the corresponding vector lane of the output accumulator will be negated. |