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  3. 40GbE TCP Offload Engine IP core (TOE40G-IP)

40GbE TCP Offload Engine IP core (TOE40G-IP)

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Product Description

40GbE TCP Offloading Engine(TOE40G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE40G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for AMD FPGA. It helps you to reduce development time. DesignGateway provide demo file for AMD FPGA boards. You can evaluate TOE40G-IP core on real board before purchasing.

Key Features and Benefits

  • TCP/IP off-loading engine for 40GBASE-SR4
  • Support IPv4 protoco
  • Support one port connection (Support Multi-session by implementing multiple cores)
  • Supports Full Duplex communication
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • Provide free evaluation bit file for FPGA Development Kits
  • Reference design is included in IP core product

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado 2019.1 Y 987 5270 34 0 0 0 300
KINTEX-U Family XCKU040 -2 Vivado 2019.1 Y 959 5321 34 0 0 0 300

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 1.0
Date Current Revision was Released Jan 01, 2019
Release Date of First Version Jan 01, 2019

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 0
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? N
Driver OS Support NA

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology None
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZCU102, ZCU106, KCU105
Industry Standard Compliance Testing Passed N
Are Test Results Available? N