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  3. 10G/25Gbit EMAC IP core for TOE IP & UDP IP

10G/25Gbit EMAC IP core for TOE IP & UDP IP

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Product Description

DG 10G25G EMAC IP implements the MAC layer for 10G/25Gb Ethernet solution. Before transmitting the packet from AXI4 stream interface (TOE10G/25G IP or UDP10G/25G IP) to XGMII interface (10G/25G Ethernet PCS/PMA), the preamble, SFD, and FCS are appended as the packet header by TenGEMAC IP. After end of packet transmission, the interframe gap is appended as the footer to be the gap size for each packet.

Key Features and Benefits

  • Low Cost Solution.It is provided with TOE/UDP10G-IP core with small additional fee. You do not need to purchase vender's EMAC core so you can reduce the cost significantly.
  • Minimized resource usage. Drastically reduce resource consumption compared with Intel MAC by omitting MAC function which is not used for DG TOE/UDP10G-IP.
  • Super Low Latency. Tx latency = 19.2nsec, Rx latency = 44.8nsec. 1/4 compared with standard MAC.

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado 2019.1 Y 307 1881 0 0 0 0 156
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado 2019.1 Y 328 1873 0 0 0 0 156
VIRTEX-7X Family XC7VX485T -2 Vivado 2019.1 Y 545 1874 0 0 0 0 156
KINTEX-7 Family XC7K325T -2 Vivado 2019.1 Y 540 1875 0 0 0 0 156
Zynq-7000 Family XC7Z045 -2 Vivado 2019.1 Y 532 1872 0 0 0 0 156
KINTEX-U Family XCKU040 -2 Vivado 2019.1 Y 314 1870 0 0 0 0 156

IP Quality Metrics

General Information

This Data was Current On Sep 04, 2024
Current IP Revision Number 1.0
Date Current Revision was Released Jul 11, 2019
Release Date of First Version Jul 01, 2019

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex-7
Software Drivers Provided? N
Driver OS Support N/A

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Other
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology None
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Other

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KCU105, ZCU102, VCU118, VC707,ZC706,KC705
Industry Standard Compliance Testing Passed N
Are Test Results Available? N