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  3. True Random Number Generator (TRNG)

True Random Number Generator (TRNG)

  • Part Number: TRNG-P200
  • Vendor: BERTEN DSP S.L.
  • Partner Tier: Elite Certified
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Product Description

The TRNG-P200 generates reliable true random numbers for any FPGA, SoC, or ASIC design targeting cryptographic applications. The physical entropy source is based on multi-phase oscillators, producing a high quality RNG. The IP core passes NIST 800-22, AIS-31 PTG.2, and Diehard test suites; and implements a complete set of health tests compliant with NIST 800-90B, FIPS 140-2, and AIS-31.

Key Features and Benefits

  • AMBA-AXI Interface
  • Portable to any FPGA or ASIC
  • Internal Fault Detection
  • Passes Diehard Battery of Tests
  • FIPS 140-2 Compliant
  • NIST 800-90B & AIS-31 Health Tests
  • NIST SP800-22 Compliant
  • Passes AIS-31 PTG.2 Test Suites
  • High-quality Entropy Source

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU5P -2 Vivado ML 2021.2 1077 4746 2 0 0 0 655
Zynq-UP-MPSoC Family XCZU7EV -1 Vivado ML 2021.2 Y 1117 4590 2 0 0 0 565
Kintex-UP Family XCKU5P -1 Vivado 2018.2 1067 4596 2 0 0 0 565
Spartan-7 Family XC7S50 -2 Vivado 2018.2 1839 4591 2 0 0 0 270
VERSAL_AI_CORE Family XCVC1802 -1 Vivado ML 2021.2 1127 4239 2 0 0 0 255
Artix-UP Family XCAU20P -2 Vivado ML 2021.2 1078 4743 2 0 0 0 685
KINTEX-7 Family XC7K70T -1 Vivado 2018.2 1843 4587 2 0 0 0 335
ARTIX-7 Family XC7A50T -2 Vivado 2018.2 1839 4591 2 0 0 0 270
VIRTEX-7X Family XC7VX550T -2 Vivado 2018.2 1831 4758 2 0 0 0 400
Zynq-7000 Family XC7Z030 -1 Vivado 2018.2 Y 1872 4588 2 0 0 0 335
Zynq-7000 Family XC7Z020 -1 Vivado 2018.2 Y 1871 4592 2 0 0 0 220
VIRTEX-U Family XCVU080 -2 Vivado 2018.2 1134 4753 2 0 0 0 405
KINTEX-U Family XCKU035 -1 Vivado 2018.2 1096 4592 2 0 0 0 350

IP Quality Metrics

General Information

This Data was Current On Mar 26, 2024
Current IP Revision Number 1.2.1280
Date Current Revision was Released Feb 19, 2024
Release Date of First Version Dec 11, 2019

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? Y
Driver OS Support Linux, Baremetal

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques UltraFast Design Methodology, Inference, Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4-Stream
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology None
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Other

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Zedboard, Trenz TE0715, UltraZed
Industry Standard Compliance Testing Passed N
Are Test Results Available? N