NVMe Streamer
- Part Number: NVMe Streamer
- Vendor: Missing Link Electronics, Inc.
- Partner Tier: Premier
Product Description
NVMe (Non-Volatile Memory Express) has become the prominent choice for connecting Solid-State Drives (SSD) when storage read/write bandwidth is key. Electrically, the NVMe protocol operates on top of PCIe; it leaves behind legacy protocols such as AHCI, and thus scales well for performance.
MLE has been integrating PCIe, and NVMe, into FPGA-based systems for a while. Now, MLE releases NVMe Streamer which is a so-called Full Accelerator NVMe host subsystem integrated into FPGAs, and most prominently into AMD Zynq Ultrascale+ MPSoC and RFSoC devices.
MLE's new NVMe Streamer is the result of many successful customer projects and responds to the embedded market's needs to make use of modern SSDs. NVMe Streamer is a fully integrated and pre-validated subsystem stack operating the NVMe protocol fully in Programmable Logic (PL) with no software running, keeping the Processing System (PS) out of this performance path. For AMD FPGAs, NVMe Streamer utilizes AMD GTH and GTY Multi-Gigabit Transceivers together with AMD PCIe Hard IP Cores for physical PCIe connectivity.
Key Features and Benefits
- Scalable to PCIe x1, x2, x4, x8 lanes.
- Compatible with PCIe Gen 1 (2.5 GT/sec), Gen 2 (5 GT/sec), Gen 3 (8 GT/sec), Gen 4 (16 GT/sec) speeds.
- Approx. 50k LUTs and 170 BRAM tiles (for AMD UltraScale+).
- Control & Status interface for IO commands and drive administration.
- PCIe Enumeration, NVMe Initialization & Identify, Queue Management.
- Fully integrated and tested NVMe Host Controller IP Core.
- Full Acceleration means "CPU-less" operation.
- Provides one or more NVMe / PCIe host ports for NVMe SSD connectivity.
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU7EV | -2 | Vivado ML 2023.1 | Y | 0 | 5277 | 201 | 9 | 20 | 4 | 250 |
IP Quality Metrics
General Information
| This Data was Current On | Dec 05, 2023 |
| Current IP Revision Number | 2023.2 |
| Date Current Revision was Released | Sep 22, 2023 |
| Release Date of First Version | Feb 21, 2020 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 6 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code, Bitstream |
| Source Code Format(s) | Verilog, VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Other |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq UltraScale+ MPSoC |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Instantiation, UltraFast Design Methodology, Other Optimization Techniques |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis / 2018.1 |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Stream, AXI4-Lite |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Constrained random testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim / 2018.1; Mentor Questa |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | ZCU106 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |