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  3. 1G Ultra-Low Latency Ethernet MAC /PCS / PMA

1G Ultra-Low Latency Ethernet MAC /PCS / PMA

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Product Description

The 1G Ultra-Low Latency Ethernet MAC / PCS / PMA is the industry leading solution for latency critical Ethernet applications. The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances. The IP core supports full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets.

Key Features and Benefits

  • Highly optimized implementation resulting in ultra-low latency and very low gate count
  • Soft PCS logic interfacing to standard SERDES
  • Compliant with the IEEE 802.3 High Speed Ethernet Standard
  • Programmable Tx and Rx path VLAN detection
  • Configurable statistics vector and collector on transmit and receive MAC/PCS data

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado ML 2023.2 Y 0 2497 0 0 0 1 250

IP Quality Metrics

General Information

This Data was Current On Oct 08, 2024
Current IP Revision Number 1.0
Date Current Revision was Released Oct 07, 2024
Release Date of First Version Feb 03, 2020

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Model Formats Other
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog, OVM System Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? N
Standard FPGA Optimization Techniques Other Optimization Techniques
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Mentor Questa; Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Reflex CES XpressVUP
Industry Standard Compliance Testing Passed N
Are Test Results Available? N