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  3. 40/100G Ultra-Low Latency Ethernet MAC/PCS + RS-FEC

40/100G Ultra-Low Latency Ethernet MAC/PCS + RS-FEC

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Product Description

The dual-rate 40/100G Ultra-Low Latency Ethernet MAC/PCS + RS-FEC is the industry leading solution for latency critical Ethernet applications. The core is designed using advanced techniques leading to unmatched, ultra-low gate count utilization and amazing latency performances. The IP core supports full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic, up to jumbo frame size, with no dropped packets. Two other versions of the IP core are also available, each supporting a single rate, i.e. 40Gbps or 100Gbps (with RS-FEC).

Key Features and Benefits

  • Highly optimized implementation resulting in ultra-low latency and very low gate
  • Built-In Reed Solomon FEC RS(528, 514) with FEC bypass and error correction bypass capabilities
  • Two other versions of the IP core are also available, each supporting a single rate, i.e. 40Gbps or 100Gbps (with RS-FEC)
  • Fully compliant with IEEE 802.3-2015 standard
  • Configurable statistics vector and collector on transmit and receive MAC/PCS data
  • Multi-rate configurable IP core supporting 40G and 100G line rate.

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado ML 2023.2 Y 0 48778 21 0 0 4 402

IP Quality Metrics

General Information

This Data was Current On Oct 08, 2024
Current IP Revision Number 1.0
Date Current Revision was Released Oct 07, 2024
Release Date of First Version Feb 03, 2020

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? N
FPGA Used on Board Virtex UltraScale+
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Mentor Questa; Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Reflex CES Xpress VUP
Industry Standard Compliance Testing Passed N
Are Test Results Available? N