40G TCP/IP Stack
- Part Number: 40G TCP/IP Stack
- Vendor: Missing Link Electronics, Inc.
- Partner Tier: Premier
Product Description
TCP/IP Full Accelerator for 40G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width, pipelined all-RTL implementation for ultra low Latency.
Key Features and Benefits
- Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
- Point-to-point or LAN capable
- Network Interface Card functionality with Bypass (optional)
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU19EG | -2 | Vivado ML 2023.1 | Y | 35460 | 166136 | 0 | 32 | 0 | 0 | 156 |
IP Quality Metrics
General Information
| This Data was Current On | Dec 05, 2023 |
| Current IP Revision Number | 2.71 |
| Date Current Revision was Released | Nov 16, 2023 |
| Release Date of First Version | Feb 04, 2019 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 2 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Bitstream, Netlist |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | N |
| FPGA Used on Board | N/A |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis; Other; Mentor Precision; Synplicity Synplify; Xilinx XST |
| Static Timing Analysis Performed? | N |
| AXI Interfaces | AXI4-Stream |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Both |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Mentor Questa; Xilinx lSim; Other |
Hardware Validation
| Validated on FPGA | N |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |