100G UDP/IP Hardware Protocol Stack Core
- Part Number: UDPIP-100G
- Vendor: CAST, Inc.
- Partner Tier: Elite Certified
Product Description
Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 100Gbps even in processor-less SoC designs. Trouble-free network operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the Address Resolution Protocol (ARP), which is critical for multiple access networks, and the Echo Request and Reply Messages (“ping”) of the Internet Control Message Protocol (ICMP) widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a Dynamic Host Configuration Server (DHCP) server. Furthermore, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN. The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated AXI4-stream interfaces, or optionally via registers accessible via an AXI4-Lite port . Up to 32 streaming interfaces are used for transmit data, and up to 32 for receive data. Each such pair of receive and transmit interfaces (a “channel”) is configured independently, with the source UDP port, destination IP address and UDP port, multicast).
Key Features and Benefits
- Up to 32 UDP channels
- Supports IPv4 without packet fragmentation, Jumbo and Super Jumbo Frames, ARP with Cache, ICMP (Ping), IGMP v3 (Multicast), UDP/IP Unicast and Multicast, DHCP, and VLAN (802.1Q)
- Run time programmable network parameters: Local, Destination and Gateway IP address, Source and Destination UDP ports, MAC address
- 512-bit data-path and AXI-Stream data interfaces
- Available pre-integrated with Intel’s 100G eMAC core
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU15EG | -1 | Vivado 2019.1 | 0 | 18053 | 82 | 0 | 0 | 0 | 250 | |
| Zynq-UP-MPSoC Family | XCZU11EG | -1 | Vivado 2019.1 | N | 0 | 9970 | 30 | 0 | 0 | 0 | 250 |
| VERSAL_AI_CORE Family | XCVC1902 | -2 | Vivado ML 2023.2 | 4457 | 16214 | 53 | 0 | 0 | 0 | 300 | |
| Kintex-UP Family | XCKU19P | -1 | Vivado ML 2023.2 | 0 | 15989 | 59 | 0 | 0 | 0 | 250 | |
| KINTEX-U Family | XCKU060 | -2 | Vivado ML 2023.2 | 0 | 16003 | 59 | 0 | 0 | 0 | 250 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 07, 2024 |
| Current IP Revision Number | 3V07N00S00 |
| Date Current Revision was Released | Dec 21, 2023 |
| Release Date of First Version | Apr 02, 2020 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 3 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Kintex UltraScale+ |
| Software Drivers Provided? | N |
| Driver OS Support | N/A |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference |
| Custom FPGA Optimization Techniques | BRAM Inference |
| Synthesis Software Tools Supported/Version | Vivado Synthesis; Synplicity Synplify; Mentor Precision |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Stream, AXI4-Lite |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Both |
| Assertions | N |
| Coverage Metrics Collected | Code, Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Cadence NC-Sim; Cadence IUS; Mentor ModelSIM; Mentor Questa; Synopsys VCS |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | KCU116 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |