10G/25G UDP/IP Hardware Protocol Stack
- Part Number: UDPIP-10G/25G
- Vendor: CAST, Inc.
- Partner Tier: Elite Certified
Product Description
The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 25Gbps even in processor-less designs.
Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination and gateway IP addresses; UDP ports; and MAC address). The core implements the ARP Protocol, which is critical for multiple access networks, and the Echo Request and Reply Messages of the ICMP widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a DHCP server. Finally, the core supports 801.1Q tagging, and is suitable for operation in a Virtual LAN.
The core is easy to integrate in systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or via registers mapped on an SoC bus.
Key Features and Benefits
- 1 to 32 UDP transmit and 1 to UDP 32 receive channels
- Run time programmable network parameters: Local, Destination and Gateway IP address, Source and Destination UDP ports, MAC address
- Protocols, IPv4 without packet fragmentation, Jumbo and Super Jumbo Frames, ARP with Cache, ICMP (Ping), IGMP v3 (Multicast), UDP/IP Unicast and Multicast, DHCP, VLAN (802.1Q)
- 64-bit data-path and AXI-Stream data interfaces
- 10/100/1000, 10G, and 25G Ethernet
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Kintex-UP Family | XCKU9P | -2 | Vivado ML 2023.1 | Y | 0 | 4203 | 8 | 0 | 0 | 0 | 400 |
| VERSAL_AI_CORE Family | XCVC1902 | -2 | Vivado ML 2023.1 | 852 | 4202 | 2 | 0 | 0 | 0 | 250 | |
| KINTEX-7 Family | XC7K325T | -1 | Vivado ML 2023.1 | Y | 1652 | 4123 | 9 | 0 | 0 | 0 | 125 |
| KINTEX-U Family | XCKU060 | -1 | Vivado ML 2023.1 | Y | 0 | 4196 | 8 | 0 | 0 | 0 | 125 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 07, 2024 |
| Current IP Revision Number | 3V07N00S00 |
| Date Current Revision was Released | Jan 09, 2024 |
| Release Date of First Version | Oct 23, 2013 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 33 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Source Code, Netlist |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Kintex UltraScale |
| Software Drivers Provided? | N/A |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference |
| Custom FPGA Optimization Techniques | BRAM Inference |
| Synthesis Software Tools Supported/Version | Vivado Synthesis; Mentor Precision; Synplicity Synplify |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Stream |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Both |
| Assertions | N |
| Coverage Metrics Collected | Code, Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Cadence NC-Sim; Cadence IUS; Mentor ModelSIM; Mentor Questa; Synopsys VCS |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | KCU105 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |