Curve25519 Key Exchange Compact IP Core
- Part Number: XIP4001C
- Vendor: Xiphera Ltd
- Partner Tier: Elite Certified
Product Description
XIP4001C from Xiphera is a compact Intellectual Property (IP) core designed for efficient key exchange using the X25519 protocol.
XIP4001C implements arithmetic on Curve25519 (see also RFC7748), and provides a security level of 128 bits.
Curve25519 is used in numerous security protocols and applications, including TLS 1.3 (Transport Layer Security).
Key Features and Benefits
- Optimized FPGA resource utilization
- Constant execution time
- Standard compliance with RFC7748
- Compatible with TLS 1.3
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU4EG | -2 | Vivado 2020.2 | Y | 517 | 517 | 1 | 1 | 1 | 0 | 463 |
| Zynq-7000 Family | XC7Z020 | -2 | Vivado 2020.2 | Y | 515 | 515 | 1 | 1 | 1 | 0 | 224 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 30, 2024 |
| Current IP Revision Number | 1.0 |
| Date Current Revision was Released | Dec 13, 2019 |
| Release Date of First Version | Dec 13, 2019 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 0 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq-7000 |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis / 2020.2 |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | None |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Mentor ModelSIM; Xilinx lSim / 2020.1 |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | ZedBoard |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |