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  3. 25GbE TCP Offload Engine IP core (TOE25G-IP)

25GbE TCP Offload Engine IP core (TOE25G-IP)

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Product Description

TOE25G-IP core (TCP Off-loading Engine) is the pure hardware logic TCP/IP protocol stack engine without CPU. TOE25G-IP provides 2.5X the performance of 10GbE over single channel fiber optic cable. Maximize performance per channel, provide better network traffic density and scalability, giving the greater cost-effective or power-efficient per BIT than traditional 10GbE/40GbE network technology. This IP product includes reference design for AMD FPGA. It helps you to reduce development time. Design Gateway provide demo file for AMD FPGA boards. You can evaluate TOE25G-IP core on real board before purchasing.

Key Features and Benefits

  • TCP/IP off-loading engine for 10/25GBASE-R
  • Support IPv4 protocol
  • Support one port connection (Support Multi-session by implementing multiple cores)
  • Supports Full Duplex communication
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmitted packet size aligned to 128-bit, bus size of transmit data
  • Total received data size aligned to 128-bit, bus size of received data
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • All pure hardware TCP/IP protocol stack
  • Simple control interface by 32-bit Register interface & Simple data interface by 128-bit FIFO interface
  • 64-bit AXI4 stream to interface for 10G/25G Ethernet MAC
  • User clock frequency must be more than or equal to 195.3125 MHz for 25Gb Ethernet
  • Support 10GbE by using DG 10G25G EMAC-IP and PCS
  • Provide free evaluation bit file for FPGA Development Kits
  • Reference design is included in IP core product

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado ML 2021.2 Y 780 3905 36 0 0 0 350
Kintex-UP Family XCKU5P -2 Vivado ML 2021.2 Y 764 3904 36 0 0 0 350
Zynq-UP-RFSoC Family XCZU28DR -2 Vivado ML 2021.2 Y 770 3914 36 0 0 0 350
VERSAL_AI_CORE Family XCVC1902 -2 Vivado ML 2021.2 Y 939 4472 35 0 0 0 350

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 1.1
Date Current Revision was Released Jul 15, 2022
Release Date of First Version Aug 05, 2020

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Versal AI Core Series
Software Drivers Provided? N
Driver OS Support NA

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KCU116, VCU118, VCK190
Industry Standard Compliance Testing Passed N
Are Test Results Available? N