2. Intellectual Property
  3. USB3.0 / USB3.2 Gen2 Host Controller

USB3.0 / USB3.2 Gen2 Host Controller

  • Part Number: COUSB312H_FPGA
  • Vendor: Corigine Inc.
  • Partner Tier: Select
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Product Description

Corigine provides USB controllers that are USB-IF certified. Corigine's SuperSpeed and Superspeed+ 3.1 USB IP is based on the USB 3.1 specification from the USB Implementers Forum (USB-IF). USB-IF certification reduces the risk of IP design errors due to specification interpretations. Corigine USB controllers are based on a next generation architecture which can fully take advantage of the latest USB features, while maintaining the smallest size, lowest power, and maximum configurability.

Key Features and Benefits

  • USB-IF Certified full-featured USB Host solution
  • Supports Superspeed+ USB 3.2 at 10Gbps. Super, High, Full speeds also supported
  • Supports 16/32/64-bit PIPE interface, 8/16-bit UTMI+ Interface and 8-bit ULPI Interface
  • Next generation USB controller architecture producing the smallest size, lowest power and maximum configurability
  • Industry standard AMBA interface, can easily integrate into an SoC
  • Highly configurable architecture to achieve the most optimized size and power
  • Compliant with xHCI specifications
  • Compatible with AMD GTX, GTH, and GTY transceivers. No external PHY is required

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU5P -1 Vivado 2020.2 0 61000 112 0 0 0 125000000

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 201812
Date Current Revision was Released Jan 02, 2018
Release Date of First Version Aug 15, 2017

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 20
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Bitstream, Netlist
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) OVM System Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex UltraScale
Software Drivers Provided? Y
Driver OS Support Linux

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Synplicity Synplify; Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KCU116
Industry Standard Compliance Testing Passed N
Are Test Results Available? N