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  3. 100GbE TCP Offload Engine IP core (TOE100G-IP)

100GbE TCP Offload Engine IP core (TOE100G-IP)

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Product Description

100GbE TCP Offloading Engine(TOE100G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE100G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for AMD FPGA. It helps you to reduce development time.

DesignGateway provides a demo file for AMD FPGA boards. You can evaluate TOE100G-IP core on a real board before purchasing.

Key Features and Benefits

  • All pure hardware TCP/IP protocol stack for 100Gbit Ethernet
  • Support IPv4 protocol
  • Support one port connection (Support Multi-session by implementing multiple cores)
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmitted packet size aligned to 512-bit, transmitted data bus size
  • Total receive data size aligned to 512-bit, received data bus size
  • Simple data interface by standard FIFO interface at 512-bit data bus, and Simple control interface by single-port RAM interface
  • AXI4 stream interface with AMD Ethernet MAC
  • Provide free evaluation bit file for FPGA Development Kits
  • Reference design is included in IP core product

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU5P -2 Vivado ML 2021.1 Y 2116 10430 535 0 0 0 330
Zynq-UP-RFSoC Family XCZU28DR -2 Vivado ML 2021.1 Y 2101 10418 535 0 0 0 330
VERSAL_AI_CORE Family XCVC1902 -2 Vivado ML 2021.1 Y 2250 11011 510 0 0 0 330

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 1.1
Date Current Revision was Released Jul 15, 2022
Release Date of First Version Feb 24, 2021

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex UltraScale+
Software Drivers Provided? N
Driver OS Support NA

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used VCK190, VCU118, KCU116, AlveoU250
Industry Standard Compliance Testing Passed N
Are Test Results Available? N