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  3. 40G UDP Offload Engine IP core (UDP40G-IP)

40G UDP Offload Engine IP core (UDP40G-IP)

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Product Description

UDP Offloading Engine IP core is a pure hardware logic solution implemented without CPU. UDP40G-IP is suitable for high performance data tranmission or broadcasting over network. This IP product includes reference design. It helps you to reduce development time and cost.

Key Features and Benefits

  • All hardware logic to achieve CPU-less system
  • Support IPv4 protocol
  • Support one port connection
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface & Simple control interface by standard register interface
  • Multicast/broadcast Tx feature customization
  • Reference design is included in IP core product

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado ML 2022.1 Y 673 3658 34 0 0 0 300
KINTEX-U Family XCKU040 -2 Vivado ML 2022.1 Y 733 3660 34 0 0 0 300

IP Quality Metrics

General Information

This Data was Current On May 31, 2024
Current IP Revision Number 2
Date Current Revision was Released Mar 07, 2024
Release Date of First Version Oct 21, 2019

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? N/A
Driver OS Support NA

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology None
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZCU102,KCU105
Industry Standard Compliance Testing Passed N
Are Test Results Available? N