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  3. QOID: QOI Lossless Image Compression Decoder

QOID: QOI Lossless Image Compression Decoder

  • Part Number: QOID
  • Vendor: CAST, Inc.
  • Partner Tier: Elite Certified
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Product Description

The QOID Core is a decoder that implements a highly efficient, low-power, lossless image decompression engine compliant with the Quite OK Image format (QOI) specification, version 1.0. The QOI algorithm compresses RGB or RGBA images with 8 bits per color without any loss. It has a compression efficiency close to that of the PNG compression, at a fraction of the computational complexity.

Capitalizing on the simplicity of the QOI algorithm, the QOID decoder core can decompress images at a very high speed and with minimal silicon resources. The core occupies approximately 200 LUTs and can decode one pixel per clock cycle. A single core instance can decompress images at rates sufficient for UHD 4k60 on an AMD Kintex UltraScale or Kintex UltraScale+.

The core is designed for ease of use and integration and adheres to coding and verification best practices. It requires no assistance from a host processor and uses simple handshake interfaces for input and output data. Technology mapping, timing closure, and scan insertion are trouble-free, as the core contains no multi-cycle or false paths and uses only rising-edge-triggered D-type flip-flops, no tri-states, and a single-clock/reset domain. Its reliability and low risk have been proven through rigorous verification and FPGA validation.

Key Features and Benefits

  • Available in VHDL or Verilog RTL source code or targeted FPGA netlist
  • Supports 24-bit RGB and optionally 32-bit RGBA
  • UHD/4k capable with just 200L UTs
  • Lossless Image Decompression per QOI Image Format

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-U Family XCKU085 -3 Vivado 2020.2 0 197 0 0 0 0 500
Kintex-UP Family XCKU15P -3 Vivado ML 2023.2 0 199 0 0 0 0 750
Spartan-7 Family XC7S15 -2 Vivado ML 2023.2 65 180 0 0 0 0 250
Artix-UP Family XCAU20P -2 Vivado ML 2023.2 0 197 0 0 0 0 650

IP Quality Metrics

General Information

This Data was Current On Apr 29, 2024
Current IP Revision Number 1v00
Date Current Revision was Released May 12, 2022
Release Date of First Version May 12, 2022

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 2
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Source Code, Netlist
Source Code Format(s) VHDL, Verilog
High-Level Model Included? Y
Model Formats C
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog, VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? N/A
Driver OS Support OS Independent

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST; Synplicity Synplify; Mentor Precision; Vivado Synthesis
Static Timing Analysis Performed? N
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Cadence NC-Sim; Cadence IUS; Mentor ModelSIM; Mentor Questa; Synopsys VCS

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N/A
Are Test Results Available? N