PNG-D - PNG Lossless Compression Decoder

  • Part Number: PNG-D
  • Vendor: CAST, Inc.
  • Partner Tier: Elite Certified

Product Description

The PNG-D core implements a lossless image decompression engine compliant with the Portable Network Graphics (PNG) file format specified in the ISO/IEC 15948 and RFC 2083 standards. The decoder core can decompress greyscale, truecolor, and palette-based PNG images with 8 and 16 bits per color. The core supports alpha channel transparency¬ and all the filters and DEFLATE compression options specified by the PNG standard. The core does not currently support the interlaced mode and images with under 8 bits per color, but these can be added on request. The easy-to-use PNG-D core operates on a standalone basis, parsing the image header and decompressing image data without a host processor's assistance. PNG-D accepts compressed data and outputs pixel data via AXI4-Stream interfaces. A separate dedicated interface provides the system with the image header and any ancillary chunks to prepare the decoded images for fur-ther processing and/or display. Moreover, the core detects, reports, and automatically recovers from various errors in the input files.


Key Features and Benefits

  • Over 100 Mpixels/s (8-bit greyscale) on Kintex® UltraScale™ and up to 200 Mpixels/s (8-bit greyscale) on Kintex® UltraScale+™ devices
  • Autonomous Operation. Requires no programming or control from the host processor.
  • AXI4-Stream Interfaces for image and compressed data
  • Detects, reports, and automatically recovers from the following error types: CRC or Adler mismatch, image or zlib header syntax error, and unsupported image format
  • Interlacing and less than 8-bit per color can be added on request
  • Both Dynamic and Static Huffman Tables
  • All five filters: Path, Average, Up, Sub, and None
  • 8-bit & 16-bit per color channel
  • All color types (Greyscale and Truecolor with or without alpha, Indexed/Palletized)
  • Supports all chunk types - Ancillary chunks are extracted and broadcasted to the system
  • Compliant with the ISO/IEC 15948 and RFC 2083 standards

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU15P -3 Vivado ML 2023.2 0 4590 15 0 0 0 181
Artix-UP Family XCAU20P -2 Vivado ML 2023.2 0 4533 15 0 0 0 153
KINTEX-U Family XCKU040 -1 Vivado ML 2023.2 0 4611 15 0 0 0 105

IP Quality Metrics

General Information

This Data was Current On May 31, 2024
Current IP Revision Number 1v10
Date Current Revision was Released Apr 15, 2024
Release Date of First Version Apr 15, 2022

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 2
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code, Netlist
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? N
FPGA Used on Board N/A
Software Drivers Provided? N
Driver OS Support OS Independent

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Synplicity Synplify; Mentor Precision; Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Cadence NC-Sim; Cadence IUS; Mentor ModelSIM; Mentor Questa; Synopsys VCS

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N/A
Are Test Results Available? N