Dense Stereo Matching IP
- Part Number: ZIA SV
- Vendor: Digital Media Professionals Inc.
- Partner Tier: Select
Product Description
Satisfy both of high accuracy and small footprint
- High accuracy( minimum average error rate is 0.8%)
- Small footprint supporting low-cost FPGA: AMD Ultrascale+ MPSoC 2CG/3CG/6CG、Zynq7000 series
- High resolution support - up to 4K
- High performance - up to 158fps
Key Features and Benefits
- Pre-Processing - Left-right image alignment / Stereo Rectification
- SGM core : Semi-Global Matching algorithm such as Parallel Unit(PU), Buffer compression, Sub-pixel interpolation and Uniqueness check
- Post-processing - Disparity image denoising such as Consistency check, Texture filter, Gap interpolation and Median filter
- Interface : AMBA AXI4 support
- Input data: 8-bit grayscale image , max resolution 3840x2160
- Output data: 8-bit/12-bit disparity map (max disparity 256 pixel with 1/16 subpixel) or 16-bit depth map
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU3CG | -1 | Vivado 2020.2 | Y | 68835 | 62350 | 130 | 16 | 0 | 0 | 200 |
| Zynq-UP-MPSoC Family | XCZU6CG | -1 | Vivado 2020.2 | Y | 66784 | 62565 | 262 | 16 | 0 | 0 | 200 |
IP Quality Metrics
General Information
| This Data was Current On | Aug 07, 2024 |
| Current IP Revision Number | 1.0 |
| Date Current Revision was Released | Apr 28, 2022 |
| Release Date of First Version | Apr 28, 2022 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 0 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | N |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq UltraScale+ MPSoC |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux OS |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | N |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | No |
| Test Methodology | Both |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Synopsys VCS |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | KV260 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |