10G Ultra-Low Latency TCP/IP and UDP/IP Offload Engine
- Part Number: TCP-010G-L-01
- Vendor: Orthogone Technologies Inc
- Partner Tier: Premier
Product Description
The high-performance TCP and UDP IP offload engine cores provide a fast and reliable solution for financial and networking applications. They address the data center industry's growing need for throughput and hardware acceleration and provide network protocol offload for applications such as financial data processing, reprogrammable Smart NICs, and high-performance computing.
Key Features and Benefits
- Store/Forward, Cut-Through Mode
- Configurable number of connections, up to 64 per endpoint
- Server-side or client-side support, per connection
- TCP congestion control via fast retransmit/recovery
- TCP support for MSS, timestamps
- TCP Retransmission buffer
- Layer 2 through Layer 4 solution comprises: ARP, IPv4, ICMP, TCP, UDP
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-U_Alveo Family | VU_ALVEO | -3 | Vivado ML 2023.2 | Y | 0 | 19770 | 60 | 0 | 0 | 0 | 322 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 08, 2024 |
| Current IP Revision Number | 1.7 |
| Date Current Revision was Released | Oct 07, 2024 |
| Release Date of First Version | Sep 19, 2022 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 1 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | N |
| Model Formats | N/A |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Virtex UltraScale+ |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux CentOS / RedHat |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Stream |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Code, Functional |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Mentor Questa; Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | Alveo |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |