A Compact Versatile Core for SHA-3-224/256/384/512 and (c)SHAKE-128/256
- Part Number: XIP3030C
- Vendor: Xiphera Ltd
- Partner Tier: Elite Certified
Product Description
XIP3030C is a compact IP core designed for versatile support of all variants of the SHA-3 hash function and related extendable-output function SHAKE as well as the SHA-3 derived function cSHAKE and its variants KMAC, TupleHash and ParallelHash.
SHA-3 and SHAKE are defined in the NIST (National Institute of Standards and Technology) standard FIPS PUB 202 and cSHAKE, KMAC, TupleHash and ParallelHash are specified in NIST Special Publication 800-185.
XIP3030C consumes only small amounts of FPGA resources that allows it to be used even in settings where resources are scarce
XIP3030C has also been successfully validated in the CAVP (Cryptographic Algorithm Validation Program) by NIST (National Institute for Standards and Technology).
Key Features and Benefits
- Minimal Resource Requirements: XIP3030C requires only 978 LUT6 in the AMD Artix 7.
- Versatile Algorithm Support: XIP3030C supports SHA-3-224/256/384/512, SHAKE-128/256, cSHAKE-128/256, KMAC, TupleHash and ParallelHash
- Secure Architecture: The execution time of XIP3030C is independent of the input values and, consequently, provides full protection against timing-based side-channel attacks.
- Standard Compliance: XIP3030C is compliant with FIPS 202 and SP 800-185.
- Easy Integration: The 64-bit interface of XIP3030C supports easy integration with software and/or additional FPGA design.
- CAVP validated
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-7000 Family | XC7Z020 | -1 | Vivado ML 2022.1 | Y | 1003 | 1003 | 1 | 0 | 1 | 0 | 152 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 30, 2024 |
| Current IP Revision Number | 1.0 |
| Date Current Revision was Released | Oct 26, 2022 |
| Release Date of First Version | Oct 26, 2022 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 0 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq UltraScale+ MPSoC |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Other Optimization Techniques |
| Custom FPGA Optimization Techniques | Logic optimized for 6-input LUTs |
| Synthesis Software Tools Supported/Version | Vivado Synthesis |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Xilinx lSim |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | Ultrazed-EV |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |