AES 256 IP core
- Part Number: AES256 IP
- Vendor: Design Gateway Co., Ltd.
- Partner Tier: Elite Certified
Product Description
AES256 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES256-IP computes 128-bit data blocks within constant 15 clock cycles. Delivering 8.53Mbps throughput per 1MHz such as 4.26 Gbps @500MHz.
Key Features and Benefits
- Support AES ECB mode standard.
- Key size 256 bit
- Support input data width128-bit.
- High-Throughput rate 4.26 Gbps @500MHz, 8.53 Mbits/MHz
- Low Latency 15 clock cycles for 128-bit data calculation
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU7EV | -2 | Vivado ML 2021.1 | Y | 212 | 1315 | 0 | 0 | 0 | 0 | 500 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | 1.02 |
| Date Current Revision was Released | Aug 29, 2022 |
| Release Date of First Version | Aug 01, 2022 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 1 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | N |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq UltraScale+ MPSoC |
| Software Drivers Provided? | N/A |
| Driver OS Support | NA |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | N |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | None |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | ZCU106 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |