25G EMAC / PCS + RS-FEC IP
- Part Number: 25GEMAC/PCS+RS-FEC IP
- Vendor: Design Gateway Co., Ltd.
- Partner Tier: Elite Certified
Product Description
The 25G EMAC/PCS + RS-FEC IP core provides a comprehensive implementation of the physical layer, including the Ethernet MAC layer, Physical Coding sublayer (PCS), and RS-FEC sublayer. The incorporation of RS-FEC in the system significantly enhances data reliability and connection stability, making it an ideal option for applications that prioritize data reliability. The demo is ready available for IP core evaluation. This demo aims to provide a simple yet comprehensive demonstration of the capabilities of The 25G EMAC/PCS + RS-FEC IP, connected to AMD Transceiver, which enables the physical and medium of the 25G Ethernet system.
Key Features and Benefits
- Outstanding nature: low latency / low resource utilization / cost effective and affordable
- Seamlessly co-operate with TOE25G-IP and UDP25G-IP
- Increase reliability via RS-FEC function; RS(528, 514, 10)
- Implement Ethernet MAC and PCS conforming IEEE 802.3
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Kintex-UP Family | XCKU5P | -2 | Vivado 2019.1 | Y | 2200 | 12590 | 3 | 0 | 0 | 0 | 390 |
| Zynq-UP-RFSoC Family | XCZU28DR | -2 | Vivado 2019.1 | Y | 2280 | 12588 | 3 | 0 | 0 | 0 | 390 |
IP Quality Metrics
General Information
| This Data was Current On | Sep 04, 2024 |
| Current IP Revision Number | 1.0 |
| Date Current Revision was Released | Jun 01, 2023 |
| Release Date of First Version | Jun 01, 2023 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 0 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | N |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Zynq UltraScale+ RFSoC |
| Software Drivers Provided? | N |
| Driver OS Support | NA |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | N |
| AXI Interfaces | AXI4 |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | No |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | N |
| Timing Verification Report Available | N |
| Simulators Supported | Xilinx lSim |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | ZCU111, KCU116 |
| Industry Standard Compliance Testing Passed | N |
| Are Test Results Available? | N |