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  3. 10Gbps QUIC Client IP Core (QUIC10GC-IP)

10Gbps QUIC Client IP Core (QUIC10GC-IP)

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Product Description

QUIC Client 10Gbps IP core (QUIC10GC-IP) is engineered from the ground up to simplify the QUIC protocol with TLS 1.3 security into pure hardware logic for FPGA-based client applications. This IP core fully offloads the CPU from handling TLS 1.3 handshakes, encrypting/decrypting payload data, and managing both QUIC and UDP/IP layers within Single IP core.

Key Features and Benefits

  • 10Gbps QUIC engine conforming to RFC9000
  • Supports the Client-side QUIC operation
  • Supports TLS1.3 cipher suite: TLS_AES_128_GCM_SHA256
  • Key exchange: X25519
  • Derive key: HKDF with SHA256
  • Encryption/decryption: AES128GCM
  • Certificate type: RSA2048
  • Signature algorithm: rsa_pss_rsae_sha256
  • Supports four streams (StreamIDs #0-3) compliant with the QUIC standard
  • Includes integrated UDP/IP and ARP protocol controllers
  • Requires an IP core clock frequency of 220 MHz as a minimum recommended frequency
  • Supports unaligned AXI4 protocol for user data interface
  • Utilizes a ring buffer technique for user memory management interface
  • Supports 32-bit MAC interface using AXI4-Stream protocol, operating at 322.266 MHz
  • Customized service options

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU7EV -2 Vivado ML 2022.1 Y 8812 47584 121 2 0 0 225

IP Quality Metrics

General Information

This Data was Current On Oct 07, 2024
Current IP Revision Number 1.0
Date Current Revision was Released Jul 02, 2024
Release Date of First Version Jul 02, 2024

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 0
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? N
Driver OS Support NA

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected None
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZCU106
Industry Standard Compliance Testing Passed N
Are Test Results Available? N