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  3. DVB-S2 LDPC/BCH Decoder/Encoder

DVB-S2 LDPC/BCH Decoder/Encoder

  • Part Number: CREONIC_CODING_DVB_S2
  • Vendor: Creonic GmbH
  • Partner Tier: Elite Certified
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Product Description

Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).

Key Features and Benefits

  • Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2).
  • Supports ACM, CCM, and VCM modes.
  • Support for short blocks (16200 bits) and long blocks (64800 bits).
  • Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, 32-APSK).
  • Support for all interleaving schemes of all modulation schemes.
  • Support for all LDPC and BCH codes as defined by the standard.
  • Decoder contains soft-decision demapper, block deinterleaver, LDPC decoder, BCH decoder, and descrambler.
  • Design-time configuration of throughput for optimal resource utilization.
  • Low-power and low-complexity design.
  • Burst-to-burst on-the-fly configuration.
  • Faster convergence due to layered LDPC decoder architecture.
  • Collection of statistic information (number of modified information bits, number of iterations, decoding successful).

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K410T -2 Vivado ML 2022.2 N 0 56160 259 7 0 0 270
KINTEX-7 Family XC7K325T -1 Vivado ML 2022.2 N 7486 19524 115 19 0 0 215
KINTEX-U Family XCKU060 -2 Vivado ML 2022.2 0 33351 156 7 0 0 340

IP Quality Metrics

General Information

This Data was Current On Aug 07, 2024
Current IP Revision Number 6.1.0
Date Current Revision was Released Feb 19, 2024
Release Date of First Version Jun 01, 2012

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? Y
Model Formats C, C++, Matlab
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? N
Commercial Evaluation Board Available? N
Software Drivers Provided? N/A

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST / 14.x; Xilinx XST / 13.x
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Both
Assertions Y
Coverage Metrics Collected Functional, Code
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Other / Aldec RivieraPRO

Hardware Validation

Validated on FPGA N
Industry Standard Compliance Testing Passed N
Are Test Results Available? N